CS5535 datasheet(194/555 Pages) NSC

194 / 555 page

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194

Revision 0.8

GLIU Register Descriptions (Continued)

5.1.2

P2D Descriptor MSRs

5.1.2.1

P2D Base Mask Descriptors (GLIU_P2D_BM[x])

P2D Base Mask Descriptor 0 (GLIU_P2D_BM0)

P2D Base Mask Descriptor 1 (GLIU_P2D_BM1)

P2D Base Mask Descriptor 2 (GLIU_P2D_BM2)

These registers set up the Physical To Device Base Mask descriptors for determining an address hit.

MSR Address

51010020h

Type

R/W

Reset Value

000000FF_FFF00000h

MSR Address

51010021h

Type

R/W

Reset Value

000000FF_FFF00000h

MSR Address

51010022h

Type

R/W

Reset Value

000000FF_FFF00000h

GLIU_P2D_BM[x] Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

PDID1_BM

RSVD

PBASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

987654

3210

PBASE_BM

PMASK_BM

GLIU_P2D_BM[x] Bit Descriptions

Bit

Name

Description

63:61

PDID_BM

Physical Descriptor Destination ID. These bits define which port to route the request to

if it is a hit based on the other settings in this register.

000: Port 0 (GLIU)

100: Port 4 (DD)

001: Port 1 (GLPCI_SB)

101: Port 5 (ACC)

010: Port 2 (USBC2)

110: Port 6 (USBC1)

011: Port 3 (ATAC)

111: Port 7 (GLCP)

PCMP_BIZ_BM

Physical Compare BIZZARO Flag.

0: Consider only transactions whose BIZZARO flag is low as a potentially valid address

hit. A low BIZZARO flag indicates a normal transaction cycle such as a memory or

I/O.

1: Consider only transactions whose BIZZARO flag is high as a potentially valid address

hit. A high BIZZARO flag indicates a ‘special’ transaction, such as a PCI Shutdown or

Halt cycle

59:40

RSVD

Reserved. Write as read.

39:20

PBASE_BM

Physical Memory Address Base. These bits form the matching value against which the

masked value of the physical address bits [31:12] are directly compared. If a match is

found, then a hit is declared, depending on the setting of the BIZZARO flag comparator.

19:0

PMASK_BM

Physical Memory Address Mask. These bits are used to mask physical address bits

[31:12] for the purposes of this hit detection.

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