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AD5384BBC-5 датащи(PDF) 27 Page - Analog Devices

номер детали AD5384BBC-5
подробное описание детали  40-Channel, 3 V/5 V, Single-Supply, Serial, 14-Bit Voltage Output DAC
PDF  36 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD5384BBC-5 датащи(HTML) 27 Page - Analog Devices

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AD5384
Rev. A | Page 27 of 36
Daisy-Chain Mode
For systems that contain several devices, the SDO pin can be
used to daisy-chain several devices together. This daisy-chain
mode can be useful in system diagnostics and in reducing the
number of serial interface lines.
By connecting DCEN (daisy-chain enable) pin high, the daisy-
chain mode is enabled. The first falling edge of SYNC starts the
write cycle. The SCLK is applied continuously to the input shift
register when SYNC is low. If more than 24 clock pulses are
applied, the data ripples out of the shift register and appears on
the SDO line. This data is clocked out on the rising edge of
SCLK and is valid on the falling edge. By connecting the SDO
of the first device to the DIN input on the next device in the
chain, a multidevice interface is constructed. 24 clock pulses are
required for each device in the system. Therefore, the total
number of clock cycles must equal 24N where N is the total
number of AD5384 devices in the chain.
When the serial transfer to all devices is complete, SYNC is
taken high. This latches the input data in each device in the
daisy-chain and prevents any further data being clocked into
the input shift register.
If the SYNC is taken high before 24 clocks are clocked into the
part, this is considered a bad frame and the data is discarded.
The serial clock may be either a continuous or a gated clock. A
continuous SCLK source can be used only if it can be arranged
that SYNC is held low for the correct number of clock cycles. In
gated clock mode a burst clock containing the exact number of
clock cycles must be used and SYNC taken high after the final
clock to latch the data.
Readback Mode
Readback mode is invoked by setting the R/W bit = 1 in the
serial input register write. With R/W = 1, Bits A5 to A0, in
association with Bits REG1 and REG0, select the register to be
read. The remaining data bits in the write sequence are don’t
cares. During the next SPI write, the data appearing on the SDO
output contains the data from the previously addressed register.
For a read of a single register, the NOP command can be used
in clocking out the data from the selected register on SDO.
Figure 28 shows the readback sequence.
For example, to read back the m register of Channel 0 on the
AD5384, the following sequence should be followed. First, write
0x404XXX to the AD5384 input register. This configures the
AD5384 for read mode with the m register of Channel 0
selected. Note that Data Bits DB13 to DB0 are don’t cares.
Follow this with a second write, a NOP condition, 0x000000.
During this write, the data from the m register is clocked out on
the SDO line, i.e., data clocked out contains the data from the m
register in Bits DB13 to DB0, and the top 10 bits contain the
address information as previously written. In readback mode,
the SYNC signal must frame the data. Data is clocked out on
the rising edge of SCLK and is valid on the falling edge of the
SCLK signal. If the SCLK idles high between the write and read
operations of a readback operation, the first bit of data is
clocked out on the falling edge of SYNC.
24
48
SCLK
SYNC
DIN
SDO
UNDEFINED
SELECTED REGISTER DATA CLOCKED OUT
NOP CONDITION
INPUT WORD SPECIFIES REGISTER TO BE READ
DB23
DB0
DB0
DB23
DB0
DB23
Figure 28. Serial Readback Operation



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