AD5384BBC-5 datasheet(31/36 Pages) AD

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AD5384

Rev. A | Page 31 of 36

MICROPROCESSOR INTERFACING

AD5384 to MC68HC11

The serial peripheral interface (SPI) on the MC68HC11 is

configured for master mode (MSTR = 1), the Clock Polarity bit

(CPOL) = 0, and the Clock Phase bit (CPHA) = 1. The SPI is

configured by writing to the SPI control register (SPCR)—see

the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK

of the AD5384, the MOSI output drives the serial data line (DIN)

of the AD5384, and the MISO input is driven from DOUT.

The SYNC signal is derived from a port line (PC7). When data

is being transmitted to the AD5384, the SYNC line is taken low

(PC7). Data appearing on the MOSI output is valid on the

falling edge of SCK. Serial data from the 68HC11 is transmitted

in 8-bit bytes with only eight falling clock edges occurring in

the transmit cycle.

MC68HC11

AD5384

MISO

MOSI

SCK

PC7

SDO

RESET

SPI/I2C

DIN

SCLK

SYNC

DVDD

Figure 32. AD5384-toMC68HC11 Interface

AD5384 to PIC16C6x/7x

The PIC16C6x/7x synchronous serial port (SSP) is configured

as an SPI master with the Clock Polarity bit = 0. This is done by

writing to the synchronous serial port control register

(SSPCON). See the PIC16/17 Microcontroller User Manual. In

this example I/O, port RA1 is being used to pulse SYNC and

enable the serial port of the AD5384. This microcontroller

transfers only eight bits of data during each serial transfer

operation; therefore, three consecutive read/write operations

could be needed, depending on the mode. Figure 33 shows the

connection diagram.

PIC16C6X/7X

AD5384

SDI/RC4

SDO/RC5

SCK/RC3

RA1

SDO

RESET

SPI/I2C

DIN

SCLK

SYNC

DVDD

Figure 33. AD5384-to-PIC16C6x/7x Interface

AD5384 to 8051

The AD5384 requires a clock synchronized to the serial data.

The 8051 serial interface must therefore be operated in Mode 0.

In this mode, serial data enters and exits through RxD, and a

shift clock is output on TxD. Figure 34 shows how the 8051 is

connected to the AD5384. Because the AD5384 shifts data out

on the rising edge of the shift clock and latches data in on the

falling edge, the shift clock must be inverted. The AD5384

requires its data to be MSB first. Since the 8051 outputs the LSB

first, the transmit routine must take this into account.

8XC51

AD5384

RxD

TxD

P1.1

SDO

RESET

SPI/I2C

DIN

SCLK

SYNC

DVDD

Figure 34. AD5384-to-8051 Interface

AD5384 to ADSP-2101/ADSP-2103

Figure 35 shows a serial interface between the AD5384 and the

ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should

be set up to operate in SPORT transmit alternate framing mode.

The ADSP-2101/ADSP-2103 SPORT is programmed through

the SPORT control register and should be configured as follows:

internal clock operation, active low framing, and 16-bit word

length. Transmission is initiated by writing a word to the Tx

ADSP-2101/

ADSP-2103

AD5384

SCK

TFS

RFS

SDO

RESET

SPI/I2C

DIN

SCLK

DVDD

SYNC

Figure 35. AD5384-to-ADSP-2101/ADSP-2103 Interface

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