AD5384BBC-5 datasheet(25/36 Pages) AD

25 / 36 page

AD5384

Rev. A | Page 25 of 36

HARDWARE FUNCTIONS

RESET FUNCTION

Bringing the RESET line low resets the contents of all internal

registers to their power-on reset state. Reset is a negative edge-

sensitive input. The default corresponds to m at full scale and to

c at zero. The contents of the DAC registers are cleared, setting

VOUT0 to VOUT39 to 0 V. The hardware reset activation time

takes 270 µs. The falling edge of RESET initiates the reset

process; BUSY goes low for the duration, returning high when

RESET is complete. While BUSY is low, all interfaces are

disabled and all LDAC pulses are ignored. When BUSY returns

high, the part resumes normal operation and the status of the

RESET pin is ignored until the next falling edge is detected.

ASYNCHRONOUS CLEAR FUNCTION

Bringing the CLR line low clears the contents of the DAC

registers to the data contained in the user configurable CLR

can be used in system calibration to load zero scale and full

scale to all channels. The execution time for a CLR is 35 µs.

BUSY AND LDAC FUNCTIONS

BUSY is a digital CMOS output that indicates the status of the

AD5384. The value of x2, the internal data loaded to the DAC

data register, is calculated each time the user writes new data to

the corresponding x1, c ,or m registers. During the calculation

of x2, the BUSY output goes low. While BUSY is low, the user

can continue writing new data to the x1, m, or c registers, but

no DAC output updates can take place. The DAC outputs are

updated by taking the LDAC input low. If LDAC goes low while

BUSY is active, the LDAC event is stored and the DAC outputs

update immediately after BUSY goes high. The user can hold

the LDAC input permanently low, in which case the DAC

outputs update immediately after BUSY goes high. BUSY also

goes low during power-on reset and when a falling edge is

detected on the RESET pin. During this time, all interfaces are

disabled and any events on LDAC are ignored. The AD5384

contains an extra feature whereby a DAC register is not updated

unless its x2 register has been written to since the last time

LDAC was brought low. Normally, when LDAC is brought low,

the DAC registers are filled with the contents of the x2 registers.

However, the AD5384 updates the DAC register only if the x2

data has changed, thereby removing unnecessary digital

crosstalk.

POWER-ON RESET

The AD5384 contains a power-on reset generator and state

machine. The power-on reset resets all registers to a predefined

state and configures the analog outputs as high impedance. The

BUSY pin goes low during the power-on reset sequencing,

preventing data writes to the device.

POWER-DOWN

The AD5384 contains a global power-down feature that puts all

channels into a low power mode and reduces the analog power

consumption to 2 µA maximum and digital power consumption

to 20 µA maximum. In power-down mode, the output amplifier

can be configured as a high impedance output or it can provide

a 100 kΩ load to ground. The contents of all internal registers

are retained in power-down mode. When exiting power-down,

the settling time of the amplifier elapses before the outputs

settles to their correct values.

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