AD5384

Rev. A | Page 15 of 36

Table 11. Pin Function Descriptions

Mnemonic

Function

VOUTx

Buffered Analog Outputs for Channel x. Each analog output is driven by a rail-to-rail output amplifier operating at a

gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω.

SIGNAL GND(1–5)

Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GND pins are tied together

internally and should be connected to the AGND plane as close as possible to the AD5384.

DAC GND(1–5)

Each group of eight channels contains a DAC_GND pin. This is the ground reference point for the internal 14-bit DAC.

These pins shound be connected to the AGND plane.

AGND(1–5)

Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be

connected externally to the AGND plane.

AVDD(1–5)

Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins are shorted internally and

should be decoupled with a 0.1 µF ceramic capacitor and a 10 µF tantalum capacitor. Operating range for the

AD5384-5 is 4.5 V to 5.5 V; operating range for the AD5384-3 is 2.7 V to 3.6 V.

DGND

Ground for All Digital Circuitry.

DVDD

Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. It is recommended that these pins be decoupled

with 0.1 µF ceramic and 10 µF tantalum capacitors to DGND.

REF GND

Ground Reference Point for the Internal Reference.

REFOUT/REFIN

The AD5384 contains a common REFOUT/REFIN pin. The default for this pin is a reference input. When the internal

reference is selected, this pin is the reference output. If the application requires an external reference, it can be

applied to this pin. The internal reference is enabled/disabled via the control register.

VOUT39/MON_OUT

This pin has a dual function. It acts a a buffered output for Channel 39 in default mode. But when the monitor

function is enabled, this pin acts as the output of a 39-to-1 channel multiplexer that can be programmed to multiplex

one of Channels 0 to 38 to the MON_OUT pin. The MON_OUT pin output impedance typically is 500 Ω and is

intended to drive a high input impedance like that exhibited by SAR ADC inputs.

SYNC/AD0

Serial Interface Mode. This is the frame synchronization input signal for the serial clocks before the addressed register

is updated.

DCEN/ AD1

Multifunction Pin. In serial interface mode, this pin acts as a daisy-chain enable in SPI mode and as a hardware

Serial Interface. Daisy-chain select input (level sensitive, active high). When high, this signal is used in conjunction

SDO

Serial Data Output in Serial Interface Mode. Three-stateable CMOS output. SDO can be used for daisy-chaining a

number of devices together. Data is clocked out on SDO on the rising edge of SCLK, and is valid on the falling edge of

SCLK.

Digital CMOS Output. BUSY goes low during internal calculations of the data (x2) loaded to the DAC data register.

During this time, the user can continue writing new data to the x1, c, and m registers, but no further updates to the

DAC registers and DAC outputs can take place. If LDAC is taken low while BUSY is low, this event is stored. BUSY also

goes low during power-on reset, and when the BUSY pin is low. During this time, the interface is disabled and any

events on LDAC are ignored. A CLR operation also brings BUSY low.

LDAC

Load DAC Logic Input (Active Low). If LDAC is taken low while BUSY is inactive (high), the contents of the input

registers are transferred to the DAC registers, and the DAC outputs are updated. If LDAC is taken low while BUSY is

active and internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when

BUSY goes inactive. However, any events on LDAC during power-on reset or on RESET are ignored.

CLR

Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is activated, all channels are updated

with the data in the CLR code register. BUSY is low for a duration of 35 µs while all channels are being updated with

the CLR code.

RESET

Asynchronous Digital Reset Input (Falling Edge Sensitive). The function of this pin is equivalent to that of the power-

on reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m,

c, and x2 registers to their default power-on values. This sequence typically takes 270 µs. The falling edge of RESET

initiates the RESET process and BUSY goes low for the duration, returning high when RESET is complete. While BUSY

is low, all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal

operation and the status of the RESET pin is ignored until the next falling edge is detected.