AD5384BBC-5 datasheet(12/36 Pages) AD

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AD5384

Rev. A | Page 12 of 36

I2C SERIAL INTERFACE

DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX,

unless otherwise noted.

Table 8.

Parameter1

Limit at TMIN, TMAX

Unit

Description

FSCL

400

kHz max

SCL clock frequency

2.5

µs min

SCL cycle time

0.6

µs min

tHIGH, SCL high time

1.3

µs min

tLOW, SCL low time

0.6

µs min

tHD,STA, start/repeated start condition hold time

100

ns min

tSU,DAT, data setup time

t62

0.9

µs max

tHD,DAT, data hold time

µs min

tHD,DAT, data hold time

0.6

µs min

tSU,STA, setup time for repeated start

0.6

µs m0in

tSU,STO, stop condition setup time

1.3

µs min

tBUF, bus free time between a STOP and a START condition

t10

300

ns max

tR, rise time of SCL and SDA when receiving

ns min

tR, rise time of SCL and SDA when receiving (CMOS-compatible)

t11

300

ns max

tF, fall time of SDA when transmitting

ns min

tF, fall time of SDA when receiving (CMOS-compatible)

300

ns max

tF, fall time of SCL and SDA when receiving

20 + 0.1Cb 3

ns min

tF, fall time of SCL and SDA when transmitting

400

pF max

Capacitive load for each bus line

1 See

Figure 6

2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of SCL’s

falling edge.

3 Cb is the total capacitance, in pF, of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD.

START

CONDITION

REPEATED

START

CONDITION

STOP

CONDITION

t11

t10

SDA

SCL

Figure 6. I 2C-Compatible Serial Interface Timing Diagram

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