AD5384BBC-5 datasheet(22/36 Pages) AD

22 / 36 page

AD5384

Rev. A | Page 22 of 36

Table 15. Gain Data Format (REG1 = 0, REG0 = 1)

DB13 to DB0

Gain Factor

1111

1110

1111

1110

0.75

1111

1110

0.5

1111

1110

0.25

0000

ON-CHIP SPECIAL FUNCTION REGISTERS (SFR)

The AD5384 contains a number of special function registers

(SFRs), as outlined in Table 16. SFRs are addressed with

REG1 = REG0 = 0 and are decoded using Address Bits A5 to A0.

Table 16. SFR Register Functions (REG1 = 0, REG0 = 0)

R/W

Function

NOP (No Operation)

Write CLR Code

Soft CLR

Soft Power-Down

Soft Power-Up

Control Register Write

Control Register Read

Monitor Channel

Soft Reset

SFR COMMANDS

NOP (No Operation)

REG1 = REG0 = 0, A5–A0 = 000000

Performs no operation but is useful in serial readback mode to

clock out data on DOUT for diagnostic purposes. BUSY pulses

low during a NOP operation.

Write CLR Code

REG1 = REG0 = 0, A5–A0 = 000001

DB13–DB0 = Contain the CLR data

Bringing the CLR line low or exercising the soft clear function

loads the contents of the DAC registers with the data contained

in the user-configurable CLR register, and sets VOUT0 to

VOUT39, accordingly. This can be very useful for setting up a

specific output voltage in a clear condition. It is also beneficial

for calibration purposes; the user can load full scale or zero

scale to the clear code register and then issue a hardware or

software clear to load this code to all DACs, removing the need

for individual writes to each DAC. Default on power-up is all 0s.

Soft CLR

REG1 = REG0 = 0, A5–A0 = 000010

DB13–DB0 = Don’t Care

Executing this instruction performs the CLR, which is

functionally the same as that provided by the external CLR pin.

The DAC outputs are loaded with the data in the CLR code

indicated by the BUSY low time.

Soft Power-Down

REG1 = REG0 = 0, A5–A0 = 001000

DB13–DB0 = Don’t Care

Executing this instruction performs a global power-down that

puts all channels into a low power mode that reduces the analog

supply current to 2 µA maximum and the digital current to

20 µA maximum. In power-down mode, the output amplifier

can be configured as a high impedance output or can provide a

100 kΩ load to ground. The contents of all internal registers are

retained in power-down mode. No register can be written to

while in power-down.

Soft Power-Up

REG1 = REG0 = 0, A5–A0 = 001001

DB13–DB0 = Don’t Care

This instruction is used to power up the output amplifiers and

the internal reference. The time to exit power-down is 8 µs. The

hardware power-down and software function are internally

combined in a digital OR function.

Soft RESET

REG1 = REG0 = 0, A5–A0 = 001111

DB13–DB0 = Don’t Care

This instruction is used to implement a software reset. All

internal registers are reset to their default values, which

correspond to m at full scale and c at zero. The contents of the

DAC registers are cleared, setting all analog outputs to 0 V. The

soft reset activation time is 135 µs.

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