ADIS16203SLASHPCBZ datasheet(21/28 Pages) AD

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ADIS16203

Rev. 0 | Page 21 of 28

MISCELLANEOUS CONTROL REGISTER

The MSC_CTRL control register governs the operation of several

miscellaneous features: using the general purpose I/O for data-ready

(DR) hardware I/O function, reversing the polarity of rotation

(clockwise vs. counter clockwise), and self-test. The control bits for

each of these functions are described in Table 21.

The operation of the data-ready hardware I/O function is very similar to

the alarm hardware I/O function (controlled through the ALM_CTRL

control register). In this case, the MSC_CTRL register can be used in

setting up one of the GPIO pins to serve as the hardware output pin

that indicates when the sampling, conversion, and processing of the

data output variables have been completed. This register provides

the ability to enable the data-ready hardware function and establish

its polarity.

The data-ready hardware I/O pin is reset automatically to an inactive

state part way through the next conversion cycle, resulting in a pulse

train with a duty cycle varying from ~15% to 35%, depending upon

the sample period setting. Upon completion of the next data processing

cycle, the data ready hardware I/O line is set to 1.

The MSC_CTRL, ALM_CTRL, and GPIO_CTRL control registers

can influence the same GPIO pins. A priority level has been established

to avoid conflicting assignments of the two GPIO pins. This priority

level is defined as MSC_CTRL and has precedence over ALM_CTRL,

which has precedence over GPIO_CTRL.

The self-test operation exercises the base accelerometer’s mechanical

structure and establishes a mechanical diagnostic test. The self-test

offers the ability to have the ADIS16203 run an internal diagnostic

test, which returns a pass/fail condition (see the STATUS register

definition of Bit 5 in Table 19). This feature also provides the ability

to observe the incline angle outputs during the self-test function,

which is nominally 37°, regardless of the incline angle of the device.

Note that a self-test changes the contents of SMPL_TIME to improve

the speed of this test. Upon completion, the ADIS16203 restores the

original contents to SMPL_TIME.

MSC_CTRL Register Definition

Address

Default1

Format

Access

0x35, 0x34

0x0000

N/A

R/W

1 Default is valid only until the first register write cycle.

The 16-bit miscellaneous control register is used in the controlling

of the self-test and data-ready hardware functions. This includes

turning on and off the self-test function, as well as configuring

the data-ready function. For the data-ready function, the written

values are nonvolatile, allowing for data recovery upon reset.

The self-test data is volatile and is set to 0s upon reset. This

Table 21. MSC_CTRL Bit Descriptions

Bit

Description

15:11

Not used

No Self-Test on Power-Up

1: No self-test on power-up or reset

0: Self-test on power-up enabled (typically requires

approximately 13 ms in high performance mode and

approximately 35 ms in low power mode with every

power-up or reset)

Reverse Rotation

1: Reverses rotation of both inclination outputs

0: Normal operation

Self-Test Enable

1: ST enabled (continuous self-test)

0: ST disabled

7:3

Not used

Data-Ready Enable

1: DR enabled

0: DR disabled

Data-Ready Polarity

1: Active high

0: Active low

Data-Ready Line Select

1: DIO1

0: DIO0

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