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ADIS16203/PCBZ датащи(PDF) 20 Page - Analog Devices |
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ADIS16203/PCBZ датащи(HTML) 20 Page - Analog Devices |
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20 / 28 page ![]() ADIS16203 Rev. 0 | Page 20 of 28 STATUS FEEDBACK The status control register within the ADIS16203 is utilized in deter- mining the present state of the device. The ability to monitor the device becomes necessary when and if the ADIS16203 has registered an alarm and/or error condition as indicated by the alarm enable (Bit 14) within the output data registers. STATUS Register Definition Address Default1 Format Access 0x3D, 0x3C 0x0000 N/A Read only 1 Default is valid only until the first register write cycle. The STATUS control register contains the alarm/error flags that indicate abnormal operating conditions. See Table 19 for each bit’s definition. Bit 0 and Bit 1 will automatically clear when the power supply is in the specified range of operation. Setting Bit 4 in the COMMAND register clears all flags. The flags are set on a continuing basis as long as the error or alarm conditions persist. Table 19. STATUS Bit Descriptions Bit Description 15:10 Not used 9 Alarm 2 Status 1: Active 0: Normal mode 8 Alarm 1 status 1: Active 0: Normal mode 7 Not used 6 Invalid Orientation 1: Invalid orientation 0: Normal mode 5 Self Test Fail 1: Self-test failure 0: Self-test pass 3 SPI Communications Failure 1: Error condition 0: Normal mode 2 Control Register Update Failed 1: Error condition 0: Normal mode. 1 Power Supply Above 3.625 V 1: Error condition 0: Normal mode 0 Power Supply Below 2.975 V 1: Error condition 0: Normal mode COMMAND CONTROL The COMMAND control register is utilized in sending global commands to the ADIS16203 device. Any one of the global commands can be implemented by simply writing 1 to its corresponding bit location. The command control register has write-only capability and is volatile. Table 20 describes each of these global commands. COMMAND Register Definition Address Default1 Format Access 0x3F, 0x3E 0x0000 N/A Write only 1 Default is valid only until the first register write cycle. Table 20. COMMAND Bit Descriptions Bit Description 15:8 Not used. 7 Software Reset Command. 6:5 Not used. 4 Clear Status Register, once per activation 3 Manual Flash Update Command. This command is utilized in updating all of the nonvolatile registers to Flash. Once the command is initiated, the supply voltage, VDD, must remain within specified limits for 50 ms to ensure proper update of the nonvolatile registers to Flash. 2 Auxiliary DAC Latch Command. This command acts to latch the AUX_DAC control register data into the auxiliary DAC upon receipt of the command. This allows for sequential loading of the upper and lower AUX_DAC data bytes via the SPI without having the auxiliary DAC transition into unwanted, intermediate states based upon the individual AUX_DAC data bytes. Once the two bytes of AUX_DAC are loaded, the DAC latch command is initiated to move the data into the auxiliary DAC itself. 1 Factory Reset Command. This command allows the user to reset the INCL_NULL register to its nominal setting (0x0000) upon receipt of the command. Data within the moving average filters is reset. As the manual Flash command (COMMAND register, Bit 3), this command stores all of the nonvolatile registers to Flash. Once the command is initiated, the supply voltage, VDD, must remain within specified limits for 50 ms to ensure proper update of the nonvolatile registers to Flash. 0 Null Command. This command loads the inclination offset register with a value that zeros out the inclination and outputs. Useful as a single command to simulta- neously zero the inclination outputs. As the manual Flash command (COMMAND register, Bit 3), this command stores all of the nonvolatile registers to Flash. Once the command is initiated, the supply voltage, VDD, must remain within specified limits for 50 ms to ensure proper update of the nonvolatile registers to Flash. |
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