ADIS16203SLASHPCBZ datasheet(18/28 Pages) AD

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ADIS16203

Rev. 0 | Page 18 of 28

SAMPLE PERIOD CONTROL

The output data variables within the ADIS16203 are sampled and

updated at a rate based upon the SMPL_TIME control register. The

sample period can be precisely controlled over more than a three-

decade range using a time base with two settings and a 7-bit binary

count. The use of a time base that varies with a ratio of 1:31 allows

for a more optimum resolution in the sample period than a straight

binary counter. This is reflected in Figure 29, where the frequency is

presented on a logarithmic scale.

Note that the sample period given is defined as the cumulative time

required to sample, process, and update all data output variables. The

data output variables are sampled as a group and in unison with one

another. Whatever update rate is selected for one signal, all output

data variables are updated at the same rate whether they are monitored

via the SPI or not.

For a sample period setting of less than 1098.9 μs (SMPL_TIME ≤

0x07), the overall power dissipation in the part rises by approx-

imately 300%.

256

10k

FREQUENCY (Hz)

192

128

100

Figure 29. SMPL_TIME Values vs. Sample Frequency

SMPL_TIME Register Definition

Address

Default1

Format

Access

0x37, 0x36

0x0008

N/A

R/W

1 Default is valid only until the first register write cycle.

The data within this register is nonvolatile, allowing for data

recovery upon reset.

Table 16. SMPL_TIME Bit Descriptions

Bit

Description

15:8

Not used.

ADC Time Base Control. The MSB and TMBS set the

time base of the acquisition system to 122.1 μs when

SR7 = 0 vs. 3.784 ms when SR7 = 1.

6:0

ADC Sample Period Count. The lower seven bits, SP6

to SP0, represent a binary count that results in the

combined sample period of the ADC when added to

one and then multiplied by the time base. (The

combined sample period is the period required to

sample and update all seven data outputs.) The

minimum setting for the lower seven bits, SP6 to SP0,

is 0x01. The overall acquisition time can be varied

from 244.2 μs to 15.51 ms in 122.1 μs increments for

TMBS = 0 and from 7.57 ms to 481 ms in 3.784 ms

increments for TMBS = 1. This equates to the sample

rate varying from 4096 SPS to 64.5 SPS for TMBS = 0

and from 132 SPS to 2.08 SPS for TMBS = 1.

FILTERING CONTROL

The ADIS16203 uses two types of filters for the output data. The

INCL_OUT and INCL_180_OUT data outputs use a Bartlett

Window function, and the SUPPLY_OUT, AUX_ADC, and

TEMP_OUT data outputs use a standard moving-averaging

filter. The number of taps set by the AVG_CNT control register

establishes the frequency response. The number of taps can be

derived from the contents of AVG_CNT using the following

equation:

CNT

AVG

The following equations characterize the expected behavior of

each filtering approach. Figure 30 and Figure 31 shows the

frequency responses of each filter approach.

Averaging:

(

)

()

sin

)

(

Bartlett Window:

( )

)

(

The primary difference in the frequency responses offered by

each approach lies in their side lobes, which are 13 dB better in

the Bartlett Windowing approach. The Bartlett Window filtering

has two times the latency of the moving average filter.

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