ZAMC4100GA2R datasheet(12/156 Pages) RENESAS

12 / 156 page

ZAMC4100 Datasheet

January 26, 2016

Table 3.20

HSDCTRL Register Bits Mapping.................................................................................................... 66

Table 3.21

HSDCTRL Register Bits Description ............................................................................................... 66

Table 3.22

HSDSTAT Register Bits Mapping.................................................................................................... 67

Table 3.23

HSDSTAT Register Bits Description................................................................................................ 67

Table 3.24

High-Side Diagnostic Bits Description ............................................................................................. 67

Table 3.25

PWMDREN Register Bits Mapping.................................................................................................. 70

Table 3.26

PWMDREN Register Bits Description ............................................................................................. 70

Table 3.27

ECMCTRL Register Bits Mapping ................................................................................................... 75

Table 3.28

ECMCTRL Register Bits Description ............................................................................................... 75

Table 3.29

ECMDIAG Register Bits Mapping.................................................................................................... 76

Table 3.30

ECMDIAG Register Bits Description................................................................................................ 76

Table 3.31

ECMOSF Diagnostic Bit Meaning.................................................................................................... 77

Table 3.32

AINCONF Register Bits Mapping .................................................................................................... 80

Table 3.33

AINCONF Register Bits Description ................................................................................................ 81

Table 3.34

ADCCTRL Register Bits Mapping.................................................................................................... 82

Table 3.35

ADCCTRL Register Bits Description ............................................................................................... 82

Table 3.36

Input MUX Control Bits Description ................................................................................................. 83

Table 3.37

ADCCONF Register Bits Mapping................................................................................................... 86

Table 3.38

ADCCONF Register Bits Description............................................................................................... 86

Table 3.39

ADCSTAT Register Bits Mapping.................................................................................................... 87

Table 3.40

ADCSTAT Register Bits Description................................................................................................ 87

Table 3.41

ADC Sample-Rate Configuration..................................................................................................... 88

Table 3.42

ADCCMPH and ADCCMPL Bits Description ................................................................................... 91

Table 3.43

AINDIAG Register Bits Mapping...................................................................................................... 93

Table 3.44

AINDIAG Register Bits Description.................................................................................................. 93

Table 3.45

External ADC Inputs Diagnostic Bits Description ............................................................................ 94

Table 3.46

LINCTRL Registers Bit Mapping..................................................................................................... 97

Table 3.47

LINCTRL Registers Bits Description................................................................................................ 98

Table 3.48

LINSTAT Register Bits Mapping...................................................................................................... 98

Table 3.49

LINSTAT Register Bits Mapping...................................................................................................... 98

Table 3.50

SBC Registers Address Map ......................................................................................................... 100

Table 4.1

MCU Memory Map......................................................................................................................... 104

Table 4.2

INFO Page 0 Structure .................................................................................................................. 107

Table 4.3

MCU Peripheral Interrupts ............................................................................................................. 111

Table 4.4

Configuration of Timer Trigger Behavior........................................................................................ 113

Table 4.5

Register [0x4000_0000] SYS_CLKCFG........................................................................................ 123

Table 4.6

Table 4.7

Register [0x4000_0008] SYS_MEMINFO ..................................................................................... 124

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