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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ZAMC4100GA2R датащи(PDF) 48 Page - Renesas Technology Corp |
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ZAMC4100GA2R датащи(HTML) 48 Page - Renesas Technology Corp |
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48 / 156 page  ZAMC4100 Datasheet © 2016 Integrated Device Technology, Inc. 48 January 26, 2016 Table 3.6 SMDCTRL Register Bits Description Bit Description 6 CPVEIFAC: “Charge Pump Voltage Error Interrupt Flags Automatic Clear” enable bit. 1 = CPVEIF in the RSTSTAT register (Table 3.1) is automatically cleared when the interrupt event is resolved. 0 = Automatic clearing of CPVEIF is disabled. 5 SEIFAC: “Supply Error Interrupt Flags Automatic Clear” enable bit. 1 = Supply error flags UVIF and OVIF in the RSTSTAT register are automatically cleared when the interrupt event is resolved. 0 = Automatic clear of supply error flags is disabled. 4 WDTPMEN: Bit for enabling the WDT during SLEEP and STANDBY Modes. 1 = WDT is enabled and running in SLEEP and STANDBY Modes. 0 = WDT is disabled in SLEEP and STANDBY Modes. 3 OVDP: “Over-Voltage Drivers Protection” enable bit. 1 = Over-voltage event automatically disables all drivers (HB, HS, ECM). 0 = The drivers are enabled even if an over-voltage event is detected. 2 UVDP: “Under-Voltage Drivers Protection” bit. 1 = Under-voltage event automatically disables all drivers (HB, HS, ECM). 0 = The drivers are enabled even if an under-voltage event is detected. 1 STBY: STANDBY Mode enable bit. 1 = Enables the STANDBY Mode. 0 = The system stays in NORMAL Mode. 0 SLEEP: SLEEP Mode enable bit. 1 = Enables the SLEEP Mode. 0 = The system stays in NORMAL Mode. |
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