ZAMC4100GA2R datasheet(68/156 Pages) RENESAS

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ZAMC4100 Datasheet

January 26, 2016

3.10. Pulse Width Modulation (PWM)

The ZAMC4100 SBC incorporates an 8-bit pulse width modulation module (PWM), which is designed to regulate

discrete power levels of the half-bridge and high-side driver’s output. The PWM module is a highly configurable

solution by the MCU via SPI.

3.10.1. Overview

The PWM block supports the following features:

•

PWM control for each half-bridge or high-side driver

•

Two or more drivers can be simultaneously controlled by a PWM block

•

When PWM control is not required, it can be disabled

•

Maximum frequency: ~1kHz

•

PWM frequency resolution: 8-bit

•

PWM duty-cycle resolution: 8-bit

Figure 3.15 PWM Block Diagram

PWMFCFG

Fosch/80

PWM

Prescaler

Comparator

8-bit

PWM Counter

PWMDCFG Shadow

PWMDCFG

HB1PWMEN

HB4PWMEN

HS1PWMEN

HS4PWMEN

HB1PWM

HB4PWM

HS1PWM

HS4PWM

PWMDREN

PWM Signal

This module has three registers as summarized below:

•

PWM frequency configuration register

PWMFCFG (Table 3.50)

•

PWM duty cycle configuration register

PWMDCFG (Table 3.50)

•

PWM driver control enable register

PWMDREN (see Table 3.25)

On power-on-reset, the value of register PWMDCFG is zero and the PWM output is continuously low; i.e. the

PWM is disabled. In order to start the PWM signal generation, the MCU should write to register PWMDCFG with a

value different than zero. The PWMDCFG register can be written at any time, but internally the duty-cycle value is

latched in a shadow register each time the PWM counter crosses zero. This guarantees a glitch-free signal at the

PWM output by avoiding duty-cycle changes within the PWM period.

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