AD9980PCB datasheet(23/44 Pages) AD

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AD9980

Rev. 0 | Page 23 of 44

Hexadecimal

Address

Read and

Write or

Read Only

Bits

Default

Value

Name

Description

0x12

R/W

0*** ****

Hsync Control

Active Hsync Override.

0 = The chip determines the active Hsync source.

1 = The active Hsync Source is set by 0x12, Bit 6.

*0** ****

Selects the source of the Hsync for PLL and sync processing. This

bit is used only if 0x12, Bit 7 is set to 1 or if both syncs are active.

0 = Hsync is from Hsync input pin.

1 = Hsync is from SOG.

**0* ****

Hsync Polarity Override.

0 = The chip selects the Hsync input polarity.

1 = The polarity of the input Hsync is controlled by 0x12, Bit 4.

This applies to both Hsync0 and Hsync1.

***1 ****

Hsync input polarity: this bit is used only if 0x12, Bit 5 is set to 1.

0 = Active low input Hsync.

1 = Active high input Hsync.

**** 1***

Sets the polarity of the Hsync output signal.

0 = Active low Hsync output.

1 = Active high Hsync output.

0x13

R/W

7:0

0010 0000

Hsync

Duration

Sets the number of pixel clocks that Hsync out is active.

0x14

R/W

0*** ****

Vsync Control

Active Vsync Override.

0 = The chip determines the active Vsync source.

1 = The active Vsync source is set by 0x14, Bit 6.

*0** ****

Selects the source of Vsync for the sync processing. This bit is used

only if 0x14, Bit 7 is set to 1.

0 = Vsync is from the Vsync input pin.

1 = Vsync is from the sync separator.

**0* ****

Vsync Polarity Override.

0 = The chip selects the input Vsync polarity.

1 = The polarity of the input Vsync is set by 0x14, Bit 4.

This applies to both Vsync0 and Vsync1.

***1 ****

Vsync input polarity: this bit is used only if 0x14, Bit 5 is set to 1.

0 = Active low input Vsync.

1 = Active high input Vsync.

**** 1***

Sets the polarity of the output Vsync signal.

0 = Active low output Vsync.

1 = Active high output Vsync.

**** *0**

0 = The Vsync filter is disabled.

1 = The Vsync filter is enabled.

This needs to be enabled when using the Hsync to Vsync counter.

**** **0*

Enables the Vsync duration block. This is designed to be used with

the Vsync filter.

0 = Vsync output duration is unchanged.

1 = Vsync output duration is set by Register 0x15.

0x15

R/W

7:0

0000 1010

Vsync Duration

Sets the number of Hsyncs that Vsync out is active. This is only

used if 0x14, Bit 1 is set to 1.

0x16

R/W

7:0

0000 0000

Precoast

The number of Hsync periods to Coast prior to Vsync.

0x17

R/W

7:0

0000 0000

Postcoast

The number of Hsync periods to Coast after Vsync.

0x18

R/W

0*** ****

Coast and

Clamp Control

Coast Source.

Selects the source of the Coast signal.

0 = Using internal Coast generated from Vsync.

1 = Using external Coast signal from external COAST pin.

*0** ****

Coast Polarity Override.

0 = The chip selects the external Coast polarity.

1 = The polarity of the external Coast signal is set by 0x18, Bit 5.

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