AD9980PCB datasheet(32/44 Pages) AD

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AD9980

Preliminary Technical Data

Rev. 0 | Page 32 of 44

0x18

Clamp Source

This bit determines the source of clamp timing. A 0

enables the clamp timing circuitry controlled by

clamp placement and clamp duration. The clamp posi-

tion and duration is counted from the leading edge of

Hsync. A 1 enables the external clamp input pin. The

three channels are clamped when the clamp signal is

active. The polarity of clamp is determined by the

clamp polarity bit. The power-up default setting

is 0.

Table 31. Clamp Source Selection Settings

Clamp Source

Result

Internally generated clamp

Externally provided clamp signal

0x18

Red Clamp Select

This bit determines whether the red channel is

clamped to ground or to midscale. The power-up

default setting is 0.

Table 32. Red Clamp Select Settings

Clamp

Result

Clamp to ground

Clamp to midscale

0x18

Green Clamp Select

This bit determines whether the green channel is

clamped to ground or to midscale. The power-up

default setting is 0.

Table 33. Green Clamp Select Settings

Clamp

Result

Clamp to ground

Clamp to midscale

0x18

Blue Clamp Select

This bit determines whether the blue channel is

clamped to ground or to midscale. The power-up

default setting is 0.

Table 34. Blue Clamp Select Settings

Clamp

Result

Clamp to ground

Clamp to midscale

0x19

7:0

Clamp Placement

An 8-bit register that sets the position of the internally

generated clamp.

When EXTCLMP = 0 (Register 0x18, Bit 4), a clamp

signal is generated internally at a position established

by the clamp placement register (0x19) and for a

duration set by the clamp duration register (0x1A).

Clamping starts a clamp placement (Register 0x19)

count of pixel periods after the trailing edge of Hsync.

The clamp placement may be programmed to

any value between 1 and 255. A value of 0 is

not supported.

The clamp should be placed during a time that the

input signal presents a stable black-level reference,

usually the back porch period between Hsync and the

image. When EXTCLMP = 1, this register is ignored.

Power-up default setting is 8.

0x1A

7:0

Clamp Duration

An 8-bit register that sets the duration of the

internally generated clamp.

When EXTCLMP = 0 (Register 0x18, Bit 4), a clamp

signal is generated internally at a position established

by the clamp placement register and for a duration set

by the clamp duration register. Clamping begins a

clamp placement (Register 0x19) count of pixel peri-

ods after the trailing edge of Hsync. The clamp dura-

tion may be programmed to any value between 1 and

255. A value of 0 is not supported.

For the best results, the clamp duration should be set

to include the majority of the black reference signal

time that follows the Hsync signal trailing edge.

Insufficient clamping time can produce brightness

changes at the top of the screen, and a slow recovery

from large changes in the average picture level (APL),

or brightness. When EXTCLMP = 1, this register is

ignored. Power-up default setting is 20 DDR.

0x1B

Clamp Polarity Override

This bit is used to override the internal circuitry that

determines the polarity of the clamp signal. The

power-up default setting is 0.

Table 35. Clamp Polarity Override Settings

Override Bit

Result

Clamp polarity determined by chip

Clamp polarity determined by user

0x1B

Input Clamp Polarity

This bit indicates the polarity of the clamp signal only

if Bit 7 of Register 0x1B = 1. The power-up default

setting is 1.

Table 36. Clamp Polarity Override Settings

CLMPOL

Result

Active low

Active high

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