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AD9980

Rev. 0 | Page 33 of 44

0x1B

Auto-Offset Enable

This bit selects between auto-offset mode and manual

offset mode (auto-offset disabled). See the section on

auto-offset operation. The power-up default setting

is 0.

Table 37. Auto-Offset Settings

Auto-Offset

Result

Auto-offset is disabled

Auto-offset is enabled (manual offset

mode)

0x1B

4:3

Auto-Offset Update Frequency

These bits control how often the auto-offset circuit is

updated (if enabled). Updating every 64 Hsyncs is

recommended. The power-up default setting is 11.

Table 38. Auto-Offset Update Mode

Clamp Update

Result

Update offset every clamp period

Update offset every 16 clamp periods

Update offset every 64 clamp periods

Update offset every Vsync periods

0x1B

2:0

Must be written to 011 for proper operation.

0x1C

7:0

TestReg0

Must be written to 0xFF for proper operation.

SOG CONTROL

0x1D

7:3

SOG Comparator Threshold

This register allows the comparator threshold of the

SOG slicer to be adjusted. This register adjusts it in

steps of 8 mV, with the minimum setting equaling

8 mV and the maximum setting equaling 256 mV. The

power-up default setting is 15 and corresponds to a

threshold value of 128 mV.

0x1D

SOG Output Polarity

This bit sets the polarity of the SOGOUT signal. The

power-up default setting is 0.

Table 39. SOGOUT Polarity Settings

SOGOUT

Result

Active low

Active high

0x1D

1:0

SOG Output Select

These register bits control the output on the SOGOUT

pin. Options are the raw SOG from the slicer (this is

the unprocessed SOG signal produced from the sync

slicer), the raw Hsync, the regenerated sync from the

sync filter that can generate missing syncs either due

to coasting or dropout, and the filtered sync which

excludes extraneous syncs not occurring within the

sync filter window. The power-up default setting is 0.

Table 40. SOGOUT Polarity Settings

SOGOUT Select

Function

Raw SOG from sync slicer (SOG0 or SOG1)

Raw Hsync (Hsync0 or Hsync1)

Regenerated sync from sync filter

Filtered sync from sync filter

INPUT AND POWER CONTROL

0x1E

Channel Select Override

This bit provides an override to the automatic input

channel selection. Power-up default setting is 0.

Table 41. Channel Source Override

Override

Result

Channel input source determined by chip

Channel input source determined by user

0x1E

Channel Select

This bit selects the active input channel if

Channel 0 data and syncs or Channel 1 data and

syncs. Power-up default setting is 0.

Table 42. Channel Select

Channel Select

Result

Channel 0 data and syncs are selected

Channel 1 data and syncs are selected

0x1E

Programmable Bandwidth

This bit selects between a low or high input

bandwidth. It is useful in limiting noise for lower

frequency inputs. The power-up default setting is 1.

Low analog input bandwidth is ~100 MHz; high

analog input bandwidth is ~200 MHz.

Table 43. Input Bandwidth Select

Input Bandwidth

Result

Low analog input bandwidth

High analog input bandwidth

0x1E

Power-Down Control Select

This bit sets whether power-down is controlled

manually or automatically by the chip. If automatic

control is selected (0x1E, Bit 4), the AD9980’s decision

is based on the status of the sync detect bits (Register

0x24, Bits 2, 3, 6, and 7). If either an Hsync or a sync-

on-green input is detected on any input, the chip

powers up, otherwise it powers down. If manual

control is desired, the AD9980 includes flexibility of

control with both a dedicated pin and a register bit.

The dedicated pin allows a hardware watchdog circuit

to control power-down, while the register bit allows

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