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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9980PCB датащи(PDF) 19 Page - Analog Devices |
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AD9980PCB датащи(HTML) 19 Page - Analog Devices |
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19 / 44 page  AD9980 Rev. 0 | Page 19 of 44 TIMING DIAGRAMS The following timing diagrams show the operation of the AD9980.The output data clock signal is created so that its rising edge always occurs between data transitions and can be used to latch the output data externally. There is a pipeline in the AD9980, which must be flushed before valid data becomes available. This means six data sets are presented before valid data is available. tPER tDCYCLE –tSKEW DATACK DATA HSOUT +tSKEW Figure 13. Output Timing DATAIN P0 P1 P2 P5 P3 P4 P9 P6 P8 P10 P11 P7 HSIN DATACLK 8 CLOCK CYCLE DELAY DATAOUT P0 P1 P2 P3 2 CLOCK CYCLE DELAY HSOUT Figure 14. 4:4:4 Timing Mode DATAIN P0 P1 P2 P5 P3 P4 P9 P6 P8 P10 P11 P7 HSIN DATACLK 8 CLOCK CYCLE DELAY CB/CROUT B0 R0 B2 R2 YOUT Y0 Y1 Y2 Y3 2 CLOCK CYCLE DELAY 1. PIXEL AFTER HSOUT CORRESONDS TO BLUE INPUT. 2. EVEN NUMBER OF PIXEL DELAY BETWEEN HSOUT AND DATAOUT (6 FOR THE AD9980). HSOUT Figure 15. 4:2:2 Timing Mode |
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