AD9980PCB datasheet(21/44 Pages) AD

21 / 44 page

AD9980

Rev. 0 | Page 21 of 44

Mode Descriptions

•

4:4:4—All channels come out with their 8 data bits at the

same time. Data is aligned to the negative edge of the clock

for easy capture. This is the normal 24-bit output mode for

RGB or 4:4:4 YCbCr.

•

4:2:2—Red and green channels contain 4:2:2 formatted

data (16 pins) with Y data on the green channel and Cb, Cr

data on the red channel. Data is aligned to the negative

edge of the clock. The blue channel contains the secondary

channel with Cb, Y, Cr, Y formatted DDR 4:2:2 data. The

data edges are aligned to both edges of the pixel clock, so

use of the 90° clock may be necessary to capture the

DDR data.

•

4:4:4 DDR—This mode puts out full 4:4:4 data on 12 bits of

the red and green channels thus saving 12 pins. The first

half (RGB [11:0]) of the 24-bit data is sent on the rising

edge and the second half (RGB [23:12]) is sent on the

falling edge. The 4:2:2 DDR data is sent on the blue

channel, as in 4:2:2 mode.

RGB [23:0] = R [7:0] + G [7:0] + B [7:0], so RGB [23:12] =

R [7:0] + G [7:4] and RGB [11:0] = G [3:0] + B [7:0]

Table 11. Output Formats

Port

Red

Green

Blue

Bit

4:4:4

Red/Cr

Green/Y

Blue/Cb

4:2:21

Cb, Cr

DDR 4:2:2

↑ Cb, Cr ↓ Y, Y

4:4:4 DDR

DDR

↑2 G [3:0]

DDR

↑ B [7:4]

DDR

↑ B [3:0]

N/A

DDR 4:2:2

↑ Cb, Cr

DDR

↓

R [7:0]

DDR

↓ G [7:4]

N/A

DDR 4:2:2

↓ Y, Y

1 For 4:2:2 modes the first item in the list is the first pixel after Hsync.

2 Arrows in the table indicate clock edge. Rising edge of clock =

↑, falling edge = ↓.

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