AD9980PCB datasheet(35/44 Pages) AD

35 / 44 page

AD9980

Rev. 0 | Page 35 of 44

0x1F

2:1

Output Drive Strength

These two bits select the drive strength for all high-

speed digital outputs (except VSOUT, A0, and the O/E

field). Higher drive strength results in faster rise/fall

times and in general makes it easier to capture data.

Lower drive strength results in slower rise/fall times

and helps reduce EMI and digitally generated power

supply noise. The power-up default setting is 10.

Table 52. Output Drive Strength

Output

Drive

Result

Low output drive strength

Medium low output drive strength

Medium high output drive strength

High output drive strength

0x1F

Output Clock Invert

This bit allows inversion of the output clock. The

power-up default setting is 0.

Table 53. Output Clock Invert

Select

Result

Noninverted pixel clock

Inverted pixel clock

0x20

7:6

Output Clock Select

These bits allow selection of optional output clocks

such as a fixed 40 MHz clock, a 2× clock, a 90° phase-

shifted clock or the normal pixel clock. The power-up

default setting is 00.

Table 54. Output Clock Select

Select

Result

Pixel clock

90° phase-shifted pixel clock

2× pixel clock

40 MHz internal clock

0x20

Output High Impedance

This bit puts all outputs (except SOGOUT) in a high impedance

state. The power-up default setting is 0.

Table 55. Output High Impedance

Select

Result

Normal outputs

All outputs (except SOGOUT) in high impedance mode

0x20

SOG High Impedance

This bit allows the SOGOUT pin to be placed in high

impedance mode. The power-up default setting is 0.

Table 56. SOGOUT High Impedance

Select

Result

Normal SOG output

SOGOUT pin is in high impedance mode

0x20

Field Output Polarity

This bit sets the polarity of the field output bit. The

power-up default setting is 1.

Table 57. Field Output Polarity

Select

Result

Active low = even field; active high = odd field

Active low = odd field; active high = even field

SYNC PROCESSING

0x20

PLL Sync Filter

This bit selects which signal the PLL uses. It can select

between either raw Hsync or SOG or filtered versions.

The filtering of the Hsync and SOG can eliminate

nearly all extraneous transitions which have tradi-

tionally caused PLL disruption. The power-up default

setting is 0.

Table 58. PLL Sync Filter Enable

Select

Result

PLL uses raw Hsync or SOG inputs

PLL uses filtered Hsync or SOG inputs

0x20

Sync Processing Input Source

This bit selects whether the sync processor uses a raw

sync or a regenerated sync for the following functions:

Coast, H/V count, field detection and Vsync duration

counts. Using the regenerated sync is recommended.

Table 59. SP Filter Enable

Select

Result

Sync processing uses raw Hsync or SOG

Sync processing uses the internally regenerated

Hsync

0x20

Must be set to 1 for proper operation

0x21

7:0

Must be set to default

0x22

7:0

Must be set to default

0x23

7:0

Sync Filter Window Width

This 8-bit register sets the window of time for the regenerated

Hsync leading edge (in 25 ns steps) when sync pulses are

allowed to pass through. Therefore with the default value of 10,

the window width is ±250 ns. The goal is to set the window

width so that extraneous pulses are rejected. (see the Sync

Processing section). As in the sync separator threshold, the

25 ns multiplier value is somewhat variable. The maximum

variability over all operating conditions is ±20% (20 ns to

30 ns).

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