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© Integrated Device Technology, Inc

December 2, 2015

843034 DATA SHEET

Table 7B. AC Characteristics, VCC = 3.3V±5%, VCCO_A = VCCO_B = VCCO_REF = 2.5V±5%, VEE = 0V, TA = 0°C to 70°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE: See Parameter Measurement Information section.

NOTE 1: Please refer to phase noise plot.

NOTE 2: Characterized with REF_OUT output disabled.

NOTE 3: Jitter performance using XTAL inputs.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 6: Characterized using worst device configuration.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

fOUT

Output Frequency

35

625

MHz

tjit(Ø)

RMS Phase Jitter (Random),

NOTE 1, 2

fOUT = 333.3MHz,

XTAL = 22.222MHz,

Integration Range:

12kHz – 20MHz

0.91

ps

tjit(cc)

Cycle-to-Cycle Jitter; NOTE 3, 4, 6

175

ps

tsk(o)

Output Skew; NOTE 2, 4, 5

120

ps

tR / tF

Output

Rise/Fall Time

LVPECL Outputs

20% to 80%

200

700

ps

REF_OUT

20% to 80%

200

700

ps

tS

Setup Time

M, N to nP_LOAD

5

ns

S_DATA to

S_CLOCK

5ns

S_CLOCK to

S_LOAD

5ns

tH

Hold Time

M, N to nP_LOAD

5

ns

S_DATA to

S_CLOCK

5ns

S_CLOCK to

S_LOAD

5ns

odc

Output Duty Cycle; NOTE 2

N Divider Value

 145

55

%

N Divider Value = 1

35

65

%

tLOCK

PLL Lock Time

200

ms