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© Integrated Device Technology, Inc

December 2, 2015

843034 DATA SHEET

Function Tables

Table 3A. Parallel and Serial Mode Function Table

NOTE:

L = LOW

H = HIGH

X = Don’t care

 = Rising edge transition

 = Falling edge transition

Table 3B. Programmable VCO Frequency Function Table

NOTE 1: These M divide values and the resulting frequencies correspond to a crystal or TEST_CLK frequency of 25MHz.

Table 3C. Programmable Output Divider Function Table (PLL Enabled)

*NOTE: X denotes Bank A or Bank B.

Inputs

Conditions

MR

nP_LOAD

M

N

S_LOAD

S_CLOCK

S_DATA

H

X

X

X

X

X

X

Reset. Forces outputs LOW.

L

L

Data

Data

X

X

X

Data on M and N inputs passed directly to the M divider

and N output divider. TEST output forced LOW.

L



Data

Data

L

X

X

Data is latched into input registers and remains loaded

until next LOW transition level or until a serial event

occurs.

LH

X

X

L



Data

Serial input mode. Shift register is loaded with data on

S_DATA on each rising edge of S_CLOCK.

LH

X

X



LData

Contents of the shift register are passed to the

M divider and N output divider.

LH

X

X



L

Data

M divider and N output divider values are latched.

L

H

X

X

L

X

X

Parallel or serial input do not affect shift registers.

LH

X

X

H



Data

S_DATA passed directly to M divider as it is clocked.

VCO Frequency

(MHz)

M Divide

256

128

64

32

16

8

4

2

1

M8

M7

M6

M5

M4

M3

M2

M1

M0

575

23

00001011

1

700

28

00001110

0

750

30

00001111

0

Inputs

N Divider Value

Output Frequency (MHz)

*NX2

*NX1

*NX0

Minimum

Maximum

0001

560

625

0012

280

375

0103

186.66

250

0

1

1

4 (default)

140

187.5

1005

112

150

1016

93.33

125

1108

70

93.75

1

1

1

16

35

46.875