ICS843034 datasheet(4/31 Pages) RENESAS

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December 2, 2015

843034 DATA SHEET

Pin Description and Pin Characteristic Tables

Table 1. Pin Descriptions

Number

Name

Type

Description

1, 41, 42,

43, 44,

45, 47, 48

M8, M0, M1,

M2,M3,

M4, M6, M7

Input

Pulldown

M divider input. Data latched on LOW-to-HIGH transition of nP_LOAD

input. LVCMOS/LVTTL interface levels.

Input

Pullup

2, 3

NB0, NB1

Input

Pullup

Determines output divider value as defined in Table 3C, Function Table.

LVCMOS/LVTTL interface levels.

4NB2

Input

Pulldown

OE_REF

Input

Pulldown

Output enable. Controls enabling and disabling of REF_OUT output.

REF_OUT is enabled when OE_REF is HIGH. REF_OUT is in high

impedance when OE_REF is LOW. OE_REF defaults to LOW.

LVCMOS/LVTTL interface levels.

OE_A

Input

Pullup

Output enable. Controls enabling and disabling of FOUTA0, nFOUTA0

outputs. LVCMOS/LVTTL interface levels.

OE_B

Input

Pullup

Output enable. Controls enabling and disabling of FOUTB0, nFOUTB0

outputs. LVCMOS/LVTTL interface levels.

8, 14

VCC

Power

Core supply pins.

9, 10

NA0, NA1

Input

Pullup

Determines output divider value as defined in Table 3C, Function Table.

LVCMOS/LVTTL interface levels.

NA2

Input

Pulldown

12, 24

VEE

Power

Negative supply pins.

TEST

Output

Test output which is Active in the serial mode of operation. Output driven

LOW in the parallel mode. LVCMOS/LVTTL interface levels.

15,

FOUTA0,

nFOUTA0

Output

Differential output for the synthesizer. LVPECL interface levels.

VCCO_A

Power

Output supply pin for FOUTA0, nFOUTA0.

18,

FOUTB0,

nFOUTB0

Output

Differential output pair for the synthesizer. LVPECL interface levels.

VCCO_B

Power

Output supply pin for FOUTB0, nFOUTB0.

REF_OUT

Output

Single-ended reference clock output. LVCMOS/LVTTL interface levels.

VCCO_REF

Power

Output supply pin for REF_OUT.

Unused

No connect.

Input

Pulldown

Active High Master Reset. When logic HIGH, the internal dividers are reset

causing the true outputs FOUTx to go low and the inverted outputs nFOUTx

to go high. When Logic LOW, the internal dividers and the outputs are

enabled. Assertion of MR does not affect loaded M, N and T values.

LVCMOS/LVTTL interface levels.

S_CLOCK

Input

Pulldown

Clocks in serial data present at S_DATA input into the shift register on the

rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.

S_DATA

Input

Pulldown

Shift register serial input. Data sampled on the rising edge of S_CLOCK.

LVCMOS/LVTTL interface levels.

S_LOAD

Input

Pulldown

Controls transition of data from shift register into the dividers.

LVCMOS/LVTTL interface levels.

VCCA

Power

Analog supply pin.

30, 31

SEL0, SEL1

Input

Pulldown

Clock select inputs. LVCMOS/LVTTL interface levels.

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