5

© Integrated Device Technology, Inc

December 2, 2015

843034 DATA SHEET

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

32

TEST_CLK

Input

Pulldown

Single-ended test clock input. LVCMOS/LVTTL interface levels.

33,

34

XTAL_IN0

XTAL_OUT0

Input

Crystal oscillator interface. XTAL_IN0 is the input, XTAL_OUT0 is the

output.

35,

36

XTAL_IN1

XTAL_OUT1

Input

Crystal oscillator interface. XTAL_IN1 is the input, XTAL_OUT1 is the

output.

37

CLK

Input

Pulldown

Non-inverting differential clock input.

38

nCLK

Input

Pullup/

Pulldown

Inverting differential clock input. VCC/2 default when left floating.

39

nP_LOAD

Input

Pulldown

Parallel load input. Determines when data present at M8:M0 is loaded into

M divider, and when data present at NA2:NA0 and NB2:NB0 is loaded into

the N output dividers. LVCMOS/LVTTL interface levels.

40

VCO_SEL

Input

Pullup

Determines whether the synthesizer is in PLL or Bypass mode.

LVCMOS/LVTTL interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

CIN

Input

Capacitance

Control

Input Pins

4pF

Clock

Input Pins

3pF

RPULLUP

Input Pullup Resistor

51

k



RPULLDOWN

Input Pulldown Resistor

51

k



ROUT

Output

Impedance

REF_OUT

VCCO_REF = 3.3V

5

7

12



Number

Name

Type

Description