DSPIC30F datasheet(99/248 Pages) MICROCHIP

99 / 248 page

 2004 Microchip Technology Inc.

Preliminary

DS70083G-page 97

dsPIC30F

12.2

Input Capture Operation During

Sleep and Idle Modes

An input capture event will generate a device wake-up

or interrupt, if enabled, if the device is in CPU Idle or

Sleep mode.

Independent of the timer being enabled, the input cap-

ture module will wake-up from the CPU Sleep or Idle

mode when a capture event occurs if ICM<2:0> = 111

and the interrupt enable bit is asserted. The same wake-

up can generate an interrupt if the conditions for pro-

cessing the interrupt have been satisfied. The wake-up

feature is useful as a method of adding extra external pin

interrupts.

12.2.1

INPUT CAPTURE IN CPU SLEEP

MODE

CPU Sleep mode allows input capture module opera-

tion with reduced functionality. In the CPU Sleep mode,

the ICI<1:0> bits are not applicable and the input cap-

ture module can only function as an external interrupt

source.

The capture module must be configured for interrupt

only on rising edge (ICM<2:0> = 111) in order for the

input capture module to be used while the device is in

Sleep mode. The prescale settings of 4:1 or 16:1 are

not applicable in this mode.

12.2.2

INPUT CAPTURE IN CPU IDLE

MODE

CPU Idle mode allows input capture module operation

with full functionality. In the CPU Idle mode, the Inter-

rupt mode selected by the ICI<1:0> bits is applicable,

as well as the 4:1 and 16:1 capture prescale settings

which are defined by control bits ICM<2:0>. This mode

requires the selected timer to be enabled. Moreover,

the ICSIDL bit must be asserted to a logic ‘0’.

the

input

capture

module

defined

ICM<2:0> = 111 in CPU Idle mode, the input capture

pin will serve only as an external interrupt pin.

12.3

Input Capture Interrupts

The input capture channels have the ability to generate

an interrupt based upon the selected number of cap-

ture events. The selection number is set by control bits

ICI<1:0> (ICxCON<6:5>).

Each channel provides an interrupt flag (ICxIF) bit. The

respective capture channel interrupt flag is located in

the corresponding IFSx Status register.

Enabling an interrupt is accomplished via the respec-

tive capture channel interrupt enable (ICxIE) bit. The

capture

interrupt

enable

bit

located

the

corresponding IEC Control register.

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