DSPIC30F datasheet(33/248 Pages) MICROCHIP

33 / 248 page

 2004 Microchip Technology Inc.

Preliminary

DS70083G-page 31

dsPIC30F

The same multiplier is used to support the MCU multi-

ply instructions which include integer 16-bit signed,

unsigned and mixed sign multiplies. Additional data

paths are provided to allow these instructions to write

the result back into the W array and X data bus (via the

W array). These paths are placed prior to the data

scaler. The IF bit in the CORCON register, therefore,

only affects the result of the MAC class of DSP instruc-

tions. All other multiply operations are assumed to be

integer operations. If the user executes a MAC instruc-

tion on fractional data without clearing the IF bit, the

result must be explicitly shifted left by the user program

after multiplication in order to obtain the correct result.

The MUL instruction may be directed to use byte or

word sized operands. Byte operands will direct a 16-bit

result, and word operands will direct a 32-bit result to

the specified register(s) in the W array.

2.5.2

DATA ACCUMULATORS AND

ADDER/SUBTRACTER

The data accumulator consists of a 40-bit adder/

subtracter with automatic sign extension logic. It can

select one of two accumulators (A or B) as its pre-

accumulation source and post-accumulation destina-

tion. For the ADD and LAC instructions, the data to be

accumulated or loaded can be optionally scaled via the

barrel shifter, prior to accumulation.

2.5.2.1

Adder/Subtracter, Overflow and

Saturation

The adder/subtracter is a 40-bit adder with an optional

zero input into one side and either true, or complement

data into the other input. In the case of addition, the

carry/borrow input is active high and the other input is

true data (not complemented), whereas in the case of

subtraction, the carry/borrow input is active low and the

other input is complemented. The adder/subtracter

generates overflow status bits SA/SB and OA/OB,

which are latched and reflected in the STATUS register:

• Overflow from bit 39: this is a catastrophic

overflow in which the sign of the accumulator is

destroyed.

• Overflow into guard bits 32 through 39: this is a

recoverable overflow. This bit is set whenever all

the guard bits bits are not identical to each other.

The adder has an additional saturation block which

controls accumulator data saturation, if selected. It

uses the result of the adder, the overflow status bits

described above, and the SATA/B (CORCON<7:6>)

and ACCSAT (CORCON<4>) mode control bits to

determine when and to what value to saturate.

Six STATUS register bits have been provided to

support saturation and overflow; they are:

OA:

AccA overflowed into guard bits

OB:

AccB overflowed into guard bits

SA:

AccA saturated (bit 31 overflow and saturation)

AccA overflowed into guard bits and saturated

(bit 39 overflow and saturation)

SB:

AccB saturated (bit 31 overflow and saturation)

AccB overflowed into guard bits and saturated

(bit 39 overflow and saturation)

OAB:

Logical OR of OA and OB

SAB:

Logical OR of SA and SB

The OA and OB bits are modified each time data

passes through the adder/subtracter. When set, they

indicate that the most recent operation has overflowed

into the accumulator guard bits (bits 32 through 39).

The OA and OB bits can also optionally generate an

arithmetic warning trap when set and the correspond-

ing overflow trap flag enable bit (OVATEN, OVBTEN) in

the INTCON1 register (refer to Section 5.0) is set. This

allows the user to take immediate action, for example,

to correct system gain.

The SA and SB bits are modified each time data

passes through the adder/subtracter but can only be

cleared by the user. When set, they indicate that the

accumulator has overflowed its maximum range (bit 31

for 32-bit saturation, or bit 39 for 40-bit saturation) and

will be saturated (if saturation is enabled). When satu-

ration is not enabled, SA and SB default to bit 39 over-

flow and thus indicate that a catastrophic overflow has

occurred. If the COVTE bit in the INTCON1 register is

set, SA and SB bits will generate an arithmetic warning

trap when saturation is disabled.

The overflow and saturation status bits can optionally

be viewed in the STATUS register (SR) as the logical

OR of OA and OB (in bit OAB) and the logical OR of SA

and SB (in bit SAB). This allows programmers to check

one bit in the STATUS register to determine if either

accumulator has overflowed, or one bit to determine if

either accumulator has saturated. This would be useful

for complex number arithmetic which typically uses

both the accumulators.

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