DSPIC30F datasheet(3/248 Pages) MICROCHIP

3 / 248 page

 2004 Microchip Technology Inc.

Preliminary

DS70083G-page 1

dsPIC30F

High Performance Modified RISC CPU:

• Modified Harvard architecture

• C compiler optimized instruction set architecture

• 84 base instructions

• 24-bit wide instructions, 16-bit wide data path

• Linear program memory addressing up to 4M

instruction words

• Linear data memory addressing up to 64 Kbytes

• Up to 144 Kbytes on-chip Flash program space

• Up to 48K instruction words

• Up to 8 Kbytes of on-chip data RAM

• Up to 4 Kbytes of non-volatile data EEPROM

• 16 x 16-bit working register array

• Three Address Generation Units that enable:

- Dual data fetch

- Accumulator write back for DSP operations

• Flexible Addressing modes supporting:

- Indirect, Modulo and Bit-Reversed modes

• Two 40-bit wide accumulators with optional

saturation logic

• 17-bit x 17-bit single cycle hardware fractional/

integer multiplier

• Single cycle Multiply-Accumulate (MAC)

operation

• 40-stage Barrel Shifter

• Up to 30 MIPs operation:

- DC to 40 MHz external clock input

- 4 MHz-10 MHz oscillator input with

PLL active (4x, 8x, 16x)

• Up to 41 interrupt sources:

- 8 user selectable priority levels

• Vector table with up to 62 vectors:

- 54 interrupt vectors

- 8 processor exceptions and software traps

Peripheral Features:

• High current sink/source I/O pins: 25 mA/25 mA

• Up to 5 external interrupt sources

•Timer module with programmable prescaler:

- Up to five 16-bit timers/counters; optionally

pair up 16-bit timers into 32-bit timer modules

• 16-bit Capture input functions

• 16-bit Compare/PWM output functions:

- Dual Compare mode available

• Data Converter Interface (DCI) supports common

audio Codec protocols, including I2S and AC’97

• 3-wire SPI™ modules (supports 4 Frame modes)

•I2C™ module supports Multi-Master/Slave mode

and 7-bit/10-bit addressing

• Addressable UART modules supporting:

- Interrupt on address bit

- Wake-up on Start bit

- 4 characters deep TX and RX FIFO buffers

• CAN bus modules

Analog Features:

• 12-bit Analog-to-Digital Converter (A/D) with:

- 100 Ksps conversion rate

- Up to 16 input channels

- Conversion available during Sleep and Idle

• Programmable Low Voltage Detection (PLVD)

• Programmable Brown-out Detection and Reset

generation

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the dsPIC30F Family Reference

Manual (DS70046). For more information on the device

instruction set and programming, refer to the dsPIC30F

Programmer’s Reference Manual (DS70030).

dsPIC30F Enhanced Flash 16-bit Digital Signal Controllers

General Purpose and Sensor Families

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