DSPIC30F datasheet(32/248 Pages) MICROCHIP

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dsPIC30F

DS70083G-page 30

Preliminary

 2004 Microchip Technology Inc.

2.5.1

MULTIPLIER

The 17 x 17-bit multiplier is capable of signed or

unsigned operation and can multiplex its output using a

scaler to support either 1.31 fractional (Q31) or 32-bit

integer results. The respective number representation

formats are shown in Figure 2-10. Unsigned operands

are zero-extended into the 17th bit of the multiplier

input value. Signed operands are sign-extended into

the 17th bit of the multiplier input value. The output of

the 17 x 17-bit multiplier/scaler is a 33-bit value which

is sign-extended to 40 bits. Integer data is inherently

represented as a signed two’s complement value,

where the MSB is defined as a sign bit. Generally

speaking, the range of an N-bit two’s complement inte-

ger is -2N-1 to 2N-1 – 1. For a 16-bit integer, the data

range is -32768 (0x8000) to 32767 (0x7FFF) including

‘0’ (see Figure 2-10). For a 32-bit integer, the data

range

-2,147,483,648

(0x8000 0000)

2,147,483,645 (0x7FFF FFFF).

When the multiplier is configured for fractional multipli-

cation, the data is represented as a two’s complement

fraction, where the MSB is defined as a sign bit and the

radix point is implied to lie just after the sign bit (QX

format). The range of an N-bit two’s complement frac-

tion with this implied radix point is -1.0 to (1 – 21-N). For

a 16-bit fraction, the Q15 data range is -1.0 (0x8000)

to 0.999969482 (0x7FFF) including ‘0’ and has a

precision of 3.01518x10-5. In Fractional mode, the

16x16 multiply operation generates a 1.31 product

which has a precision of 4.65661 x 10-10.

FIGURE 2-10:

16-BIT INTEGER AND FRACTIONAL MODES

Certain multiply operations always operate on signed

data. These include the

MAC/MSC,

MPY[.N]

and

ED[AC]

instructions. The 40-bit adder/subtracter may

also optionally negate one of its operand inputs to

change the result sign (without changing the oper-

ands). This is used to create a multiply and subtract

(MSC), or multiply and negate (MPY.N) operation.

In the special case when both input operands are 1.15

fractions and equal to 0x8000 (-110), the result of the

multiplication is corrected to 0x7FFFFFFF (as the

closest approximation to +1) by hardware before it is

used.

It should be noted that with the exception of DSP mul-

tiplies, the dsPIC30F ALU operates identically on inte-

ger and fractional data. Namely, an addition of two

integers will yield the same result (binary number) as

the addition of two fractional numbers. The only differ-

ence is how the result is interpreted by the user. How-

ever, multiplies performed by DSP operations are

different. In these instructions, data format selection is

made with the IF bit (CORCON<0>) and US bits

(CORCON<12>), and it must be set accordingly (‘0’ for

Fractional mode, ‘1’ for Integer mode in the case of the

IF bit, and ‘0’ for Signed mode, ‘1’ for Unsigned mode

in the case of the US bit). This is required because of

the implied radix point used by dsPIC30F fractions. In

Integer mode, multiplying two 16-bit integers produces

a 32-bit integer result. However, multiplying two 1.15

values generates a 2.30 result. Since the dsPIC30F

uses 1.31 format for the accumulators, a DSP multiply

in Fractional mode also includes a left shift by one bit to

keep the radix point properly aligned. This feature

reduces the resolution of the DSP multiplier to 2-30, but

has no other effect on the computation.

Different Representations of 0x4001

Integer:

214

213

212

211 ....

0x4001

= 214 + 20 = 16385

1.15 Fractional:

2-15

0x4001

= 2-1 + 2-15 = 0.500030518

. 2-1 2-2 2-3 . . .

-20

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