DSPIC30F datasheet(51/248 Pages) MICROCHIP

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 2004 Microchip Technology Inc.

Preliminary

DS70083G-page 49

dsPIC30F

4.3

Instruction Stalls

4.3.1

INTRODUCTION

In order to maximize data space, EA calculation and

operand fetch time, the X data space read and write

accesses are partially pipelined. The latter half of the

read phase overlaps the first half of the write phase of

an instruction, as shown in Section 2.0.

Address register data dependencies, also known as

‘Read After Write’ (RAW) dependencies may, there-

fore, arise between successive read and write opera-

tions using common registers. They occur across

instruction boundaries and are detected by the

hardware.

An example of a RAW dependency is a write operation

(in the current instruction) that modifies W5, followed

by a read operation (in the next instruction) that uses

W5 as a source address pointer. W5 will not be valid for

the read operation until the earlier write completes.

This problem is resolved by stalling the instruction exe-

cution for one instruction cycle, thereby allowing the

write to complete before the next read is started.

4.3.2

RAW DEPENDENCY DETECTION

During the instruction pre-decode, the core determines

if any address register dependency is imminent across

an instruction boundary. The stall detection logic com-

pares the W register (if any) used for the destination EA

of the instruction currently being executed, with the W

fetched instruction. As the W registers are also memory

mapped, the stall detection logic also derives an SFR

address from the W register being used by the destina-

tion EA, and determines whether this address is being

issued during the write phase of the instruction

currently being executed.

When it observes a match between the destination and

source registers, a set of rules is applied to decide

whether or not to stall the instruction by one cycle.

Table 4-2 lists out the various RAW conditions which

cause an instruction execution stall.

TABLE 4-2:

RAW DEPENDENCY RULES (DETECTION BY HARDWARE)

Destination

Addressing Mode

Using Wn

Source Addressing

Mode Using Wn

Status

Examples

(Wn = W2)

Direct

No Stall ADD.w

W0, W1, W2

MOV.w

W2, W3

Direct

Indirect

Stall

ADD.w

W0, W1, W2

MOV.w

[W2], W3

Direct

Indirect with Pre- or

Post-Modification

Stall

ADD.w

W0, W1, W2

MOV.w

[W2++], W3

Indirect

Direct

No Stall ADD.w

W0, W1, [W2]

MOV.w

W2, W3

Indirect

No Stall ADD.w

W0, W1, [W2]

MOV.w

[W2], W3

Indirect

Stall

ADD.w

W0, W1, [W2] ; W2=0x0004 (mapped W2)

MOV.w

[W2], W3

; (i.e. if W2 = addr. of

W2)

Indirect

Indirect with Pre- or

Post-Modification

No Stall ADD.w

W0, W1, [W2]

MOV.w

[W2++], W3

Indirect

Indirect with Pre- or

Post-Modification

Stall

ADD.w

W0, W1, [W2] ; W2=0x0004 (mapped W2)

MOV.w

[W2++], W3

; (i.e. if W2 = addr. of

W2)

Indirect with Pre- or

Post-Modification

Direct

No Stall ADD.w

W0, W1, [W2++]

MOV.w

W2, W3

Indirect with Pre- or

Post-Modification

Indirect

Stall

ADD.w

W0, W1, [W2++]

MOV.w

[W2], W3

Indirect with Pre- or

Post-Modification

Indirect with Pre- or

Post-Modification

Stall

ADD.w

W0, W1, [W2++]

MOV.w

[W2++], W3

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