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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SW52212 датащи(PDF) 57 Page - Silicon Laboratories |
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SW52212 датащи(HTML) 57 Page - Silicon Laboratories |
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57 / 71 page  10.2 Si52212 Land Pattern The following figure illustrates the land pattern details for the Si52212 in a 64-Lead 9 x 9 mm QFN package. The table lists the values for the dimensions shown in the illustration. Figure 10.2. 64L 9 x 9 mm QFN Land Pattern Table 10.2. PCB Land Pattern Dimensions Dimension mm C1 8.90 C2 8.90 E 0.50 X1 0.30 Y1 0.85 X2 5.30 Y2 5.30 Notes: General 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabri- cation Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 mm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all pads. 4. A 3x3 array of 1.25 mm square openings on a 1.80 mm pitch should be used for the center ground pad. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Data Sheet Packaging silabs.com | Building a more connected world. Rev. 1.0 | 57 |
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