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SW52212 датащи(PDF) 49 Page - Silicon Laboratories

номер детали SW52212
подробное описание детали  12/8/4/2-Output PCI-Express Gen 1/2/3/4/5 and SRIS Clock Generator
PDF  71 Pages
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производитель  SILABS [Silicon Laboratories]
домашняя страница  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SW52212 датащи(HTML) 49 Page - Silicon Laboratories

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9.2 Si52208 Pin Descriptions
1
2
3
4
5
6
7
8
9
10
11
12
VDDA
GNDA
SS_EN
PWRGD/PWRDNb
VDDX
XIN/CLKIN
XOUT
VDDR
REF / SA
VSSR
SDA
SCLK
36
35
25
34
33
32
31
30
29
28
27
26
VDD_IO
NC
OE_4b
DIFF_4b
DIFF_4
VDD
VDD_IO
OE_2b
Si52208
NC
DIFF_3b
DIFF_3
OE_3b
Figure 9.2. 48-pin QFN
Pin
Name
Type
Description
1
VDDA
PWR
Analog Power Supply.
2
GNDA
PWR
Analog Ground.
3
SS_EN
I
Spread spectrum enable pin. 0 = –0.25% spread, mid= Off, 1 = –0.5%
spread (This pin has an internal 100 kΩ pull-up).
4
PWRGD/PWRDNb
I, PU
Active low input pin asserts power down (PDb) and disables all outputs.
(This pin has an internal 100 kΩ pull-up). Refer also to settings of Byte 2,
Bit2 and Bit3 for REF. Settings for Bit3 (REF_OE) will take precedence
for REF.
5
XIN/CLKIN
I
25.00 MHz crystal input or 25 MHz Clock Input.
6
XOUT
O
25.00 MHz crystal output. Float XOUT if using only CLKIN (Clock input).
7
VDDX
PWR
Power supply for crystal.
8
VDDR
PWR
Power supply for REF output.
9
REF /SA
O/I
REF = 25 MHz LVCMOS output. SA = Address select for I2C. When part
is powered up, SA will be latched to select the I2C address. Refer to Ta-
ble 8.1 SA State on First Application of PWRGD/PWRDNb on page 32.
Refer also to 5.14 REF/SA Pin for termination. (This pin has an internal
60 kΩ pull-up.)
10
VSSR
GND
Power supply for crystal.
11
SDA
I/O
I2C compatible SDATA.
12
SCLK
I
I2C compatible SCLOCK.
Data Sheet
Pin Descriptions
silabs.com | Building a more connected world.
Rev. 1.0 | 49



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