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SW52212 датащи(PDF) 46 Page - Silicon Laboratories |
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SW52212 датащи(HTML) 46 Page - Silicon Laboratories |
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46 / 71 page ![]() 9. Pin Descriptions 9.1 Si52212 Pin Descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDDA GNDA NC GND SS_EN PWRGD/PWRDNb GND XIN/CLKIN XOUT VDDX VDDR REF / SA VSSR SDA SCLK FS 48 47 37 36 35 34 33 46 45 44 43 42 41 40 39 38 GND DIFF_7b DIFF_7 OE_7b OE_6b DIFF_6b DIFF_6 GND VDD DIFF_5b DIFF_5 OE_5b OE_4b DIFF_4b DIFF_4 GND Si52212 Figure 9.1. 64-Pin QFN Table 9.1. Si52212 64-Pin QFN Descriptions Pin # Name Type Description 1 VDDA PWR Analog Power Supply. 2 GNDA PWR Analog Ground. 3 NC No connect. 4 GND GND Ground. 5 SS_EN I Spread spectrum enable pin. 0 = –0.25% spread, mid= Off, 1= –0.5% spread (This pin has an internal 100 kΩ pull-up). 6 PWRGD/ PWRDNb I, PU Active low input pin asserts power down (PDb) and disables all outputs (This pin has an internal 100 kΩ pull-up). Refer also to settings of Byte 2, Bit2 and Bit3 for REF. Settings for Bit3 (REF_OE) will take precedence for REF. 7 GND GND Ground. 8 XIN/CLKIN I 25.00 MHz crystal input or 25 MHz Clock Input. 9 XOUT O 25.00 MHz crystal output. Float XOUT if using only CLKIN (Clock input). 10 VDDX PWR Power supply for crystal. 11 VDDR PWR Power supply for REF output. 12 REF /SA O/I REF = 25 MHz LVCMOS output. SA = Address select for I2C. When part is pow- ered up, SA will be latched to select the I2C address. Refer to Table 8.1 SA State on First Application of PWRGD/PWRDNb on page 32. Refer also to 5.14 REF/SA Pin for termination. (This pin has an internal 60 kΩ pull-up.) Data Sheet Pin Descriptions silabs.com | Building a more connected world. Rev. 1.0 | 46 |
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