NAND04GR3B datasheet(22/59 Pages) STMICROELECTRONICS

22 / 59 page

NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B

22/59

Page Program

The Page Program operation is the standard oper-

ation to program data to the memory array. Gener-

ally, data is programmed sequentially, however

the device does support Random Input within a

page.

The memory array is programmed by page, how-

ever partial page programming is allowed where

any number of Bytes (1 to 2112) or Words (1 to

1056) can be programmed.

The maximum number of consecutive partial page

program operations allowed in the same page is

eight. After exceeding this a Block Erase com-

mand must be issued before any further program

operations can take place in that page.

Sequential Input. To input data sequentially the

addresses must be sequential and remain in one

block.

For Sequential Input each Page Program opera-

tion consists of five steps (see Figure 12.):

one bus cycle is required to setup the Page

Program (Sequential Input) command (see

Table 10.)

four or five bus cycles are then required to

input the program address (refer to Table 6.

and Table 7.)

the data is then loaded into the Data Registers

one bus cycle is required to issue the Page

Program confirm command to start the P/E/R

Controller. The P/E/R will only start if the data

has been loaded in step 3.

the P/E/R Controller then programs the data

into the array.

Random Data Input. During a Sequential Input

operation, the next sequential address to be pro-

grammed can be replaced by a random address,

by issuing a Random Data Input command. The

following two steps are required to issue the com-

mand:

one bus cycle is required to setup the Random

Data Input command (see Table 10.)

two bus cycles are then required to input the

new column address (refer to Table 6.)

Random Data Input can be repeated as often as

required in any given page.

Once the program operation has started the Sta-

tus Register can be read using the Read Status

the Status Register will only flag errors for bits set

to '1' that have not been successfully programmed

to '0'.

During the program operation, only the Read Sta-

tus Register and Reset commands will be accept-

ed, all other commands will be ignored.

Once the program operation has completed the P/

E/R Controller bit SR6 is set to ‘1’ and the Ready/

Busy signal goes High.

The device remains in Read Status Register mode

until another valid command is written to the Com-

mand Interface.

Figure 12. Page Program Operation

I/O

Address Inputs

SR0

ai08659

Data Input

10h

70h

80h

Page Program

Setup Code

Confirm

Code

Read Status Register

Busy

tBLBH2

(Program Busy time)

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