NAND04GR3B datasheet(7/59 Pages) STMICROELECTRONICS

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NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B

SUMMARY DESCRIPTION

The NAND Flash 2112 Byte/ 1056 Word Page is a

family of non-volatile Flash memories that uses

NAND cell technology. The devices range from

512 Mbits to 8 Gbits and operate with either a 1.8V

or 3V voltage supply. The size of a Page is either

2112 Bytes (2048 + 64 spare) or 1056 Words

(1024 + 32 spare) depending on whether the de-

vice has a x8 or x16 bus width.

The address lines are multiplexed with the Data In-

put/Output signals on a multiplexed x8 or x16 In-

put/Output bus. This interface reduces the pin

count and makes it possible to migrate to other

densities without changing the footprint.

Each block can be programmed and erased over

100,000 cycles. To extend the lifetime of NAND

Flash devices it is strongly recommended to imple-

ment an Error Correction Code (ECC).

The devices have hardware and software security

features:

■

A Write Protect pin is available to give a

hardware protection against program and

erase operations.

■

A Block Locking scheme is available to

provide user code and/or data protection.

The devices feature an open-drain Ready/Busy

output that can be used to identify if the Program/

Erase/Read (P/E/R) Controller is currently active.

The use of an open-drain output allows the Ready/

Busy pins from several memories to be connected

to a single pull-up resistor.

A Copy Back Program command is available to

optimize the management of defective blocks.

When a Page Program operation fails, the data

can be programmed in another page without hav-

ing to resend the data to be programmed.

Each device has Cache Program and Cache Read

features which improve the program and read

throughputs for large files. During Cache Program-

ming, the device loads the data in a Cache Regis-

ter while the previous data is transferred to the

Page Buffer and programmed into the memory ar-

ray. During Cache Reading, the device loads the

data in a Cache Register while the previous data

is transferred to the I/O Buffers to be read.

All devices have the Chip Enable Don’t Care fea-

ture, which allows code to be directly downloaded

by a microcontroller, as Chip Enable transitions

during the latency time do not stop the read oper-

ation.

Two options are available for the NAND Flash

2112 Byte/ 1056 Word Page family:

■

Automatic Page 0 Read at Power-up, which

allows the microcontroller to directly download

the boot code from page 0.

■

A Unique Identifier (serial number), which

allows each device to be uniquely identified.

The Unique Identifier options is subject to an NDA

(Non Disclosure Agreement) and so not described

in the datasheet. For more details of this option

contact your nearest ST Sales office.

The devices are available in the following packag-

es:

■

TSOP48 (12 x 20mm) for all products

■

USOP48 (12 x 17 x 0.65mm) for 512Mb

and1Gb products

■

VFBGA63 (9.5 x 12 x 1mm, 0.8mm pitch) for

512Mb and 1Gb products

■

TFBGA63 (9.5 x 12 x 1.2mm, 0.8mm pitch) for

2Gb Dual Die products

■

LFBGA63 (9.5 x 12 x 1.4mm, 0.8mm pitch) for

8Gb Quadruple Die products.

For information on how to order these options refer

to Table 31., Ordering Information Scheme. De-

vices are shipped from the factory with Block 0 al-

ways valid and the memory content bits, in valid

blocks, erased to ’1’.

See Table 2., Product Description, for all the de-

vices available in the family.

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