TC35679FSG-002

2018-01-17

17

4.3.3.

Frame Format

TC35679 supports the following format:



Number of data bits:

8 bits (LSB first)



Parity bit:

no parity



Stop bit:

1 stop bit



Flow control:

RTSX/CTSX

Figure 4-6 shows UART data frame.

Figure 4-6 UART data frame

4.3.4.

Flow Control Function

Hardware flow control is available when TC35679 UART interface is assigned to GPIO5 to GPIO8 (GPIO5, 6, 13, 14) as four-wire

start-stop synchronization data transfer. Transmit flow control (CTSX) and receive flow control (RTSX). Figure 4-7 shows signals

input and output direction.

Figure 4-7 UART connection example

CTSX (Clear to Send) input signal is used for UART transmitting. Low input indicates the peer device (for example, the host in the

Figure 4-7) is ready to receive data, and TC35679 sends data if it has data to transmit. On the other hand, TC35679 stops

transmitting on the basis of UART unit frame when CTSX input is high.

RTSX (Request to Send) output signal is used for UART receiving. Low output indicates TC35679 is ready to receive data and

requests data to the peer device. TC35679 outputs RTSX low when ready to receive data. When the UART becomes busy and

cannot receive data, TC35679 outputs RTSX high, and stops UART communication on the basis of UART unit frame.

Response time of UART transmitting and receiving to flow control signals is between 1 frame to 4 frames depending on the baud

rate and internal process status of frame.

TC35679

UART Request To Send (RTSX)

UART Clear To Send (CTSX)

UART Received Data (RX)

UART Transmitted Data (TX)

HOST CPU

UART Transmit data:

TX

UART Transmit flow

control: CTSX

1

LSB

2

3

4

5

6

MSB

Start bit

Stop bit

UART Receive data:

RX

UART Receive flow

control: RTSX

1

LSB

2

3

4

5

6

MSB

Start bit

Stop bit

Over Sampling (× 12 to 17) /bit

1

2

3

4

5

6

7

8

9

10