TC35679FSG-002

2018-01-17

41

5.7.3.

SPI Interface

Table 5-12 SPI Interface

Symbols

Items

Min

Typ.

Max

Unit

tSPICLKCYC

SPI clock cycle

154

—

—

ns

tSPICLKHPW

SPI clock high pulse width

77

—

—

ns

tSPICLKLPW

SPI clock low pulse width

77

—

—

ns

tSPICSS

SPI chip select setup time

38

—

—

ns

tSPICSH

SPI chip select hold time

77

—

—

ns

tSPIIW

SPI transfer idle pulse width

54

—

—

ns

tSPIAS

SPI address setup time

38

—

—

ns

tSPIAH

SPI address hold time

77

—

—

ns

tSPIDS

SPI data setup time

38

—

—

ns

tSPIDH

SPI data hold time

77

—

—

ns

Note: SPI Interface operates on the basis of 1/n frequency of half the frequency of ARM® Cortex®-M0 core clock (6.5 MHz for 13

MHz core clock)

Figure 5-4 SPI Interface timing diagram

SCLK

ｔSPICSS

ｔSPIAS

ｔSPIAH

A7

ｔSPICSH

A6

A5

A4

WR

A0

D15

D14

D1

D0

A7

A6

SCS

DOUT

Write

ｔSPICLKHPW

ｔSPICLKLPW

ｔSPIDS

ｔSPIDH

ｔSPIIW

SCLK

ｔSPICSS

ｔSPIAS

ｔSPIAH

A7

ｔSPICSH

A6

A5

A4

WR

A0

D15

A7

A6

SCS

DIN

Read

ｔSPICLKHPW

ｔSPICLKLPW

ｔSPIDS

ｔSPIDH

ｔSPIIW

ｔSPICLKCYC

ｔSPICLKCYC

D14

D0

D1