LT8607 datasheet(13/20 Pages) AD

13 / 20 page

LTC9111

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

Note that, during classification, the STBY pin capacitor

serves as a charge reservoir to keep the chip operational

when either the PSE or PD are pulling the port voltage

low to signal a logical zero. Any external load on the STBY

pin during classification may discharge the capacitor and

cause brownout. There should be no external load on the

STBY pin during classification.

External MOSFET Switch and Inrush Control

The GATE and OUT pins allow the LTC9111 to drive an

external MOSFET (M1, Figure 7) as an inrush controller

and load switch. An internal charge pump allows the GATE

pin to be driven above the input voltage to enhance an

external N-channel MOSFET. The gate driver turns on the

external MOSFET upon entering the MDI_POWER2 state

by sourcing IGATE_UP into the GATE pin. A capacitor CGATE,

installed between the GATE pin and the GND pin, will pro-

duce a linear ramp at OUT and determine the inrush current

based on the total bulk capacitance CBULK. Use Equation

1 to ensure that the inrush current does not exceed the

maximum PD current for the corresponding class.

CGATE >> 2 • CBULK • (IGATEUP MAX/ICLASS MAX) (1)

CGATE

CBULK

RGATE

LTC9111

GATE

GND

OUT

9111 F07

Figure 7. Inrush Control

During inrush, there can be significant transient power

dissipation in the external MOSFET; SOA capability must

be considered in selecting the pass device.

Any load present at the OUT pin before inrush is com-

plete will also contribute to the total PD current observed

at the connector; this may necessitate slower inrush (i.e.,

larger CGATE). The EN logic output can be used to ensure

that application load does not contribute to the PD current

until the external MOSFET switch is enhanced and inrush is

complete. The EN pin does not go high until GATE exceeds

IN by VEN_ASSERT, at which point inrush is complete.

A resistor, RGATE, in series with CGATE is recommended for

robustness. As an example, a fault which shorts the OUT

pin to ground instantaneously while power is applied will

pull the source of the external MOSFET to ground while

CGATE maintains high voltage at the GATE pin, causing

stress on the gate of the external MOSFET. A resistor value

of RGATE = 10k will effectively decouple the gate of the

MOSFET from the capacitor in such a scenario.

When the external MOSFET switch M1 is turned off

(because the PD exited the MDI_POWER2 state), the

GATE pin is pulled to the OUT pin with a pull-down cur-

rent of IOUT_SLEEP. Once the MOSFET has been turned

off (i.e., GATE = OUT) there is an internal pull-down trickle

current, IOUT_SLEEP, on the OUT pin which helps ensure

that the GATE and OUT pins settle to ground.

PD INPUT CAPACITANCE/SNUBBER NETWORK

The LTC9111 requires a bypass capacitance between the

IN pin and ground. In order to avoid forming a highly

resonant LC tank with the coupling magnetics, a snub-

ber network should be used as shown in Figure 8. LPODL

is the equivalent differential inductance of the power

coupling network.

LPODL

LTC9111

9111 F08

C1≅3•C2

R1≅

LPODL

C1+C2

Figure 8. Snubber Network

IEEE 802.3cg specifies a maximum PD input capacitance

of 400nF during classification. This ensures sufficient

bandwidth for SCCP. Note that the PHY coupling capaci-

tors and any additional snubber network on the cable side

are also included in this budget.

A well damped snubber network with a total capacitance

(C1 + C2) of at least 150nF will generally suffice. The

voltage coefficient of the capacitor and operating voltage

should be taken into consideration, as small package

ceramic capacitors will generally provide only a fraction of

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