LT8607 datasheet(9/20 Pages) AD

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LTC9111

Rev. 0

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Subsequently, the PSE removes full operating voltage if

power becomes unavailable or if MFVS is not detected

by the PSE. As the port voltage drops below VOFF, the

LTC9111 enters the DISCONNECT state and the applica-

tion is disabled by de-asserting the EN pin. Once the PSE

has discharged the port voltage to the range of VSLEEP,

the LTC9111 enters the WAKEUP state. Thereafter, the

same sequence may be repeated to return the port to its

full operating voltage. Figure 3 provides a simplified state

diagram. In the following sections, each state is described

in more detail.

RESET

WAKEUP

MDI_POWER1

MDI_POWERDELAY

MDI_POWER2

DISCONNECT

CLASSIFICATION

SCCP RESET PULSE

VPD < VSIG_EN

TSCCP_WATCHDOG

VPD < VSIG_DIS

VPD > VSIG_DIS

VPD > VON

VPD < VOFF

TSPWR_DLY EXPIRED AND VPD > VON

9111 F03

Figure 3. Simplified PD State Machine

RESET

Upon initial application of voltage, the LTC9111 begins in

the RESET state. The LTC9111 ramps its internal supply

and turns on one of the external low-side polarity cor-

rection MOSFETs, according to the input polarity sensed

at the SNS1 and SNS2 pins. Once the low-side polari-

ty-correcting MOSFET has been enhanced, the LTC9111

proceeds to the WAKEUP state.

WAKEUP

In the WAKEUP state, the LTC9111 presents the wakeup

signature in the form of a pull-down current, IWAKEUP_PD

(typically 1.55mA). The wakeup signature alerts the PSE

to the presence of a PD. The PSE responds by sourcing

a detection probe current. Since the LTC9111 supports

classification, it does not present a constant-voltage phys-

ical detection signature. A compliant PSE limits the port

voltage to around 5V in the absence of a PD detection sig-

nature. After a mandated delay (maximum 3.11ms), the

PSE proceeds to classification. The PSE initiates classifi-

cation by sending a reset pulse. The LTC9111 detects the

reset pulse and advances to the CLASSIFICATION state.

CLASSIFICATION

During classification, the LTC9111 responds to PSE com-

mands as defined by SCCP. The protocol is explained in

detail below (see Power Class and SCCP section). The

PSE, in its assigned time slot, pulls down on the cable

to transmit a logic low or pulls up on the cable (typically

5V to 5.5V) to transmit a logic high. The LTC9111, in its

assigned time slot, pulls down on the cable to transmit

a logic low or releases the cable to transmit a logic high.

The LTC9111 monitors the voltage at the SNS1 and SNS2

pins for serial data input and drives external MOSFETs

using the SCCP pin to pull-down the cable voltage when

transmitting a logic low.

Power cannot be delivered over the cable during pull-

down time slots. During these periods, the LTC9111

maintains its state and continues operating by drawing

current from the capacitor on the STBY pin. The voltage

at the IN pin may collapse transiently during transmission

of a logic low, depending on the leakage of the rectifying

diodes and other factors. As such, the internal path from

IN to STBY is designed to block reverse current during

these periods and thus prevent the voltage on the STBY

pin reservoir capacitor from collapsing.

After a successful classification, the PSE starts a controlled

ramp of the port voltage. The LTC9111 transitions to the

MDI_POWER1 state when the voltage exceeds VSIG_DIS.

The LTC9111 maintains a watchdog timer, TSCCP_

WATCHDOG in the CLASSIFICATION state. If a fault occurs

during classification or the PSE does not apply power

upon completion of SCCP, the LTC9111 will return to the

WAKEUP state after TSCCP_WATCHDOG.

OPERATION

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