LT8607 datasheet(11/20 Pages) AD

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LTC9111

Rev. 0

For more information www.analog.com

CLASS CONFIGURATION

The LTC9111 uses the CLASSC ternary pin and the

CLASSV binary pin to configure the Power Class. The

class configuration setting determines the VON and VOFF

thresholds for state machine navigation and is reported to

the PSE during classification. The CLASSC and CLASSV

pin configurations corresponding to each class are shown

in Table 2.

Table 2. LTC9111 Class Configuration

PD CLASS

CLASSV

CLASSC

GND

FLOAT

GND

STBY

GND

STBY

FLOAT

STBY

SCCP INITIALIZATION

Every SCCP bit communication begins with a reset pulse,

issued by the PSE, followed by a presence pulse response

from the PD (see Figure 4). The PSE begins the reset pulse

by pulling the port voltage below VTL for time tRSTL and

then pulling up to VPUP. The PD detects the reset pulse

and waits for time tPDH before pulling down for time tPDL.

This is called the PD presence pulse. The PSE samples to

identify a presence pulse at time tMSP starting from the end

of reset pulse. Once the PSE has confirmed the presence of

the PD, it continues with either a write or a read operation.

SCCP WRITE SLOT

The PSE begins a write operation by pulling down the

port voltage to VTL (see Figure 5). When writing a 0, the

PSE pulls down for time tW0L. When writing a 1, the PSE

pulls down for time tW1L. The PD detects the falling edge

and samples the port voltage after tSSW to determine the

bit polarity.

SCCP READ SLOT

The PSE begins a read operation by pulling below VTL

for tW1L (see Figure 6). If sending a 0 to the PSE, the PD

detects the pull-down by the PSE and pulls down imme-

diately for tR0L. If sending a 1 to the PSE, the PD does not

pull-down the port and allows the PSE to pull-up after tW1L.

The PSE samples the port voltage after tMSR, measured

from from PSE pull-down, in order to determine the bit.

PACKET SUPPORT

TheLTC9111supportsandrespondstotheSCRATCHPAD_

READ command from the PSE; this includes the PD Class

(as configured with the CLASSC and CLASSV pins) and

the PD Type (E).

MAINTAIN FULL VOLTAGE SIGNATURE (MFVS)

While a port is powered on, a compliant PSE monitors the

port for the presence of a minimum load, called MFVS. If

MFVS is not detected, PSE will remove the power to the

PD. Specifically, a powered PD must draw a minimum of

11mA, for at least 10ms, every 300ms in order to stay

powered on. The LTC9111 has a low operating current

and will not meet the criteria for MFVS on its own. For

PD applications in which the quiescent load may be less

than the MFVS threshold, an appropriate minimum load

may need to be added e.g., on the OUT pin.

A compliant PSE may recognize currents as low as

2.5mA as a valid MFVS. Thus, for the PD application

to ensure removal of power (e.g., because it has been

locally disabled), the PD must reduce its quiescent current

below 2.5mA.

EXTERNAL COMPONENT SELECTION

STBY Bias Supply

An internal linear regulator produces a nominal 3.5V sup-

ply at the STBY pin. It is used to power internal control

circuitry. Bypass the STBY pin with a capacitance of 2.2µF

placed near the pin. In case of a ceramic chip capacitor,

the effective capacitance with a bias of 3.5V should be >

1.8µF. An 0805 or larger capacitor is recommended.

OPERATION

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