CS47L85 datasheet(27/370 Pages) CIRRUS

27 / 370 page

CS47L85

Rev 4.3

Test Conditions

DBVDD1 = DBVDD2 = DBVDD3 = DBVDD4 = CPVDD1 = AVDD = LDOVDD = 1.8V, CPVDD2 = 1.2V

DCVDD = FLLVDD = 1.2V (powered from LDO1), MICVDD = 2.5V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V,

TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MICVDD Charge Pump and Regulator (CP2 and LDO2)

Output voltage

VMICVDD

0.9

2.7

3.3

Programmable output voltage step

size

LDO2_VSEL=00h to 14h

(0.9V to 1.4V)

LDO2_VSEL=14h to 27h

(1.4V to 3.3V)

100

Maximum output current

Start-up time

4.7µF on MICVDD

1.5

2.5

Frequency Locked Loop (FLL1, FLL2, FLL3)

Output frequency

FLL output as SYSCLK

or ASYNCCLK source

98.3

MHz

FLL output as

DSPCLK source

135

150

Lock Time

FREF = 32kHz,

FOUT = 147.456MHz

FREF = 12MHz,

FOUT = 147.456MHz

RESET pin Input

RESET input pulse width

(To trigger a Hardware Reset, the

RESET input must be asserted for

longer than this duration)

µs

Test Conditions

The following electrical characteristics are valid across the full range of recommended operating conditions.

Device Reset Thresholds

AVDD Reset Threshold

VAVDD

VAVDD rising

1.66

VAVDD falling

1.06

1.44

DCVDD Reset Threshold

VDCVDD

VDCVDD rising

1.04

VDCVDD falling

0.49

0.66

DBVDD1 Reset Threshold

VDBVDD1

VDBVDD1 rising

1.66

VDBVDD1 falling

1.06

1.44

Note that the reset thresholds are derived from simulations only, across all operational and process corners.

Device performance is not assured outside the voltage ranges defined in the “Recommended Operating Conditions” section. Refer to this

section for the CS47L85 power-up sequencing requirements.

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