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CS47L85 датащи(PDF) 25 Page - Cirrus Logic

номер детали CS47L85
подробное описание детали  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 датащи(HTML) 25 Page - Cirrus Logic

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CS47L85
Rev 4.3
25
Test Conditions
DBVDD1 = DBVDD2 = DBVDD3 = DBVDD4 = CPVDD1 = AVDD = LDOVDD = 1.8V, CPVDD2 = 1.2V
DCVDD = FLLVDD = 1.2V (powered from LDO1), MICVDD = 2.5V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V,
TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Microphone Bias (MICBIAS1, MICBIAS2, MICBIAS3, MICBIAS4)
Note - No capacitor on MICBIASn
Note - In regulator mode, it is required that VMICVDD - VMICBIAS > 200mV
Minimum Bias Voltage
VMICBIAS
Regulator mode
(MICBn_BYPASS=0)
Load current
≤ 1.0mA
1.5
V
Maximum Bias Voltage
2.8
V
Bias Voltage output step size
0.1
V
Bias Voltage accuracy
-5%
+5%
V
Bias Current
Regulator mode
(MICBn_BYPASS=0),
VMICVDD - VMICBIAS >200mV
2.4
mA
Bypass mode
(MICBn_BYPASS=1)
5.0
Output Noise Density
Regulator mode
(MICBn_BYPASS=0),
MICBn_LVL = 4h,
Load current = 1mA,
Measured at 1kHz
50
nV/
Hz
Integrated noise voltage
Regulator mode
(MICBn_BYPASS=0),
MICBn_LVL = 4h,
Load current = 1mA,
100Hz to 7kHz, A-weighted
4
µVrms
Power Supply Rejection Ratio
(DBVDDn, LDOVDD, CPVDD1,
AVDD)
PSRR
100mV (peak-peak) 217Hz
90
dB
100mV (peak-peak) 10kHz
80
Load capacitance
Regulator mode
(MICBn_BYPASS=0),
MICBn_EXT_CAP=0
50
pF
Regulator mode
(MICBn_BYPASS=0),
MICBn_EXT_CAP=1
1.8
4.7
µF
Output discharge resistance
MICBn_ENA=0,
MICBn_DISCH=1
2
kΩ



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