CS47L85 datasheet(12/370 Pages) CIRRUS

12 / 370 page

CS47L85

Rev 4.3

PIN NO

NAME

TYPE

DESCRIPTION

L13

SLIMDAT

Digital Input / Output

SLIM Bus Data input / output

N12

SPKCLK1/

GPIO37

Digital Input / Output

Digital speaker (PDM) 1 clock output / GPIO37.

GPIO output is selectable CMOS or Open Drain;

SPKCCLK output is CMOS.

M11

SPKDAT1/

GPIO39

Digital Input / Output

Digital speaker (PDM) 1 data output / GPIO39.

GPIO output is selectable CMOS or Open Drain;

SPKDAT output is CMOS.

P11

SPKCLK2/

GPIO38

Digital Input / Output

Digital speaker (PDM) 2 clock output / GPIO38.

GPIO output is selectable CMOS or Open Drain;

SPKCLK output is CMOS.

N11

SPKDAT2/

GPIO40

Digital Input / Output

Digital speaker (PDM) 2 data output / GPIO40.

GPIO output is selectable CMOS or Open Drain;

SPKDAT output is CMOS.

SPKGNDLN

Supply

Left speaker driver ground (Return path for SPKVDDL).

See note.

SPKGNDLP

Supply

Left speaker driver ground (Return path for SPKVDDL).

See note.

SPKGNDRN

Supply

Right speaker driver ground (Return path for SPKVDDR).

See note.

SPKGNDRP

Supply

Right speaker driver ground (Return path for SPKVDDR).

See note.

SPKOUTLN

Analogue Output

Left speaker negative output

SPKOUTLP

Analogue Output

Left speaker positive output

SPKOUTRN

Analogue Output

Right speaker negative output

SPKOUTRP

Analogue Output

Right speaker positive output

SPKTST1

Analogue Output

Test function (recommend no external connection)

SPKTST2

Analogue Output

Test function (recommend no external connection)

P1, P2

SPKVDDL

Supply

Left speaker driver supply

J1, J2

SPKVDDR

Supply

Right speaker driver supply

D13, H1

SUBGND

Supply

Substrate ground

TCK

Digital Input

JTAG clock input.

Internal pull-down holds this pin at logic 0 for normal operation.

TDI

Digital Input

JTAG data input.

Internal pull-down holds this pin at logic 0 for normal operation.

TDO

Digital Output

JTAG data output

TMS

Digital Input

JTAG mode select input.

Internal pull-down holds this pin at logic 0 for normal operation.

TRST

Digital Input

JTAG Test Access Port reset (active low).

Internal pull-down holds this pin at logic 0 for normal operation.

External connection to DGND is recommended, if the JTAG interface

function is not required.

VREFC

Analogue Output

Bandgap reference external capacitor connection

Note:

Separate P/N ground connections are provided for each speaker driver channel; this provides flexible support for current monitoring and output

protection circuits. If this option is not used, then the respective ground connections should be tied together on the PCB.

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