CS47L85 datasheet(78/370 Pages) CIRRUS

78 / 370 page

CS47L85

Rev 4.3

5-BAND PARAMETRIC EQUALISER (EQ)

The digital core provides four EQ processing blocks as illustrated in Figure 27. A 4-input mixer is associated with each EQ.

The 4 input sources are selectable in each case, and independent volume control is provided for each path. Each EQ block

supports 1 output.

The EQ provides selective control of 5 frequency bands as described below.

The low frequency band (Band 1) filter can be configured either as a peak filter or a shelving filter. When configured as a

shelving filter, is provides adjustable gain below the Band 1 cut-off frequency. As a peak filter, it provides adjustable gain

within a defined frequency band that is centred on the Band 1 frequency.

The mid frequency bands (Band 2, Band 3, Band 4) filters are peak filters, which provide adjustable gain around the

respective centre frequency.

The high frequency band (Band 5) filter is a shelving filter, which provides adjustable gain above the Band 5 cut-off frequency.

EQnMIX_VOL2

EQnMIX_VOL3

EQnMIX_VOL4

EQnMIX_VOL1

EQnMIX_SRC1

EQnMIX_SRC3

EQnMIX_SRC4

EQnMIX_SRC2

EQ1 (50h)

EQ2 (51h)

EQ3 (52h)

EQ4 (53h)

5-band Equaliser

CS47L85 supports 4 EQ blocks, ie. n = 1, 2, 3 or 4

Figure 27 Digital Core EQ Blocks

The EQ1, EQ2, EQ3 and EQ4 mixer control registers (see Figure 27) are located at register addresses R2176 (880h) through

to R2207 (89Fh).

The full list of digital mixer control registers (Register R1600 through to R3192) is provided in a separate document - see

“Register Map” for further information. Generic register definitions are provided in Table 8.

The *_SRCn registers select the input source(s) for the respective EQ processing blocks. Note that the selected input

source(s) must be configured for the same sample rate as the EQ to which they are connected. Sample rate conversion

functions are available to support flexible interconnectivity -

see “Asynchronous Sample Rate Converter (ASRC)” and

“Isochronous Sample Rate Converter (ISRC)”.

The bracketed numbers in Figure 27,

e.g.,”(50h)” indicate the corresponding *_SRCn register setting for selection of that

signal as an input to another digital core function.

The EQ blocks should be kept disabled (EQn_ENA=0) if SYSCLK is not enabled. The *_SRCn registers for all digital core

functions should be held at 00h if SYSCLK is not enabled. SYSCLK must be present and enabled before selecting other

values for these registers. See “Clocking and Sample Rates” for further details (including requirements for reconfiguring

SYSCLK while digital core functions are enabled).

The sample rate for the EQ function is configured using the FX_RATE register - see Table 22. Note that the EQ, DRC and

LHPF functions must all be configured for the same sample rate. Sample rate conversion is required when routing the EQ

signal paths to any signal chain that is asynchronous and/or configured for a different sample rate.

The FX_RATE register should not be changed if any of the associated *_SRCn registers is non-zero. The associated

*_SRCn registers should be cleared to 00h before writing a new value to FX_RATE. A minimum delay of 125us should be

allowed between clearing the *_SRCn registers and writing to the FX_RATE register. See Table 22 for further details.

The control registers associated with the EQ functions are described in Table 10.

The cut-off or centre frequencies for the 5-band EQ are set using the coefficients held in the registers identified in Table 9.

These coefficients are derived using tools provided in Cirrus Logic

’s WISCE™ evaluation board control software; please

contact your local Cirrus Logic representative for more details.

CS47L85 датащи(PDF) 78 Page - Cirrus Logic

CS47L85 датащи(HTML) 78 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL