CS47L85 datasheet(16/370 Pages) CIRRUS

16 / 370 page

CS47L85

Rev 4.3

RECOMMENDED OPERATING CONDITIONS

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Digital Core and FLL supply range

See notes 3, 4, 5, 6, 7

DCVDD, FLLVDD

1.14

1.2

1.26

Digital supply range (I/O)

See note 8

DBVDD1, DBVDD2,

DBVDD3, DBVDD4

1.71

3.6

LDO supply range

See note 3

LDOVDD

1.71

1.8

1.89

Charge Pump supply range

CPVDD1

1.71

1.8

1.89

CPVDD2

1.14

1.2

1.26

Speaker supply range

SPKVDDL, SPKVDDR

2.4

5.5

Analogue supply range

See notes 9, 10

AVDD

1.71

1.8

1.89

Analogue supply range (FLL)

See note 4

FLLVDD

1.14

1.2

1.26

Microphone Bias supply

See note 11

MICVDD

0.9

2.5

3.78

Ground

See note 1

DGND, AGND, CPGND,

SPKGNDL, SPKGNDR,

SUBGND

Power supply rise time

See notes 12 to 17

DCVDD

2000

µs

LDOVDD

50000

All other supplies

Operating temperature range

-40

°C

Notes:

The impedance between DGND, AGND, CPGND and SUBGND should be less than 0.1

Ω. The impedance between SPKGNDL, SPKGNDR

and SUBGND should be less than 0.2

Ω.

There are no switch-on power sequencing requirements; the supplies may be enabled in any order.

When powering down the device, if DCVDD is powered using the internal LDO (LDO1), then the LDO must be disabled, or else RESET

¯¯¯¯¯¯

must be asserted (low), before the LDOVDD supply is removed. There are no other switch-off power sequencing requirements.

The DCVDD and FLLVDD pins should be tied together. The associated power domain is referred to as DCVDD.

An internal LDO (powered by LDOVDD) can be used to provide the DCVDD and FLLVDD supplies.

‘Sleep’ mode is supported when DCVDD is below the limits noted, provided AVDD and DBVDD1 are present.

It is recommended to connect a 4.7

Ω resistor in series with the FLLVDD pin connection. Note that the minimum voltage limit applies at the

supply end of the 4.7

Ω resistor in this case.

If the SLIMbus interface is enabled, then the maximum DBVDD1 voltage is 1.98V.

The AVDD1 and AVDD2 pins should be tied together. The associated power domain is referred to as AVDD.

10. The AGND1 and AGND2 pins should be tied together. The associated ground domain is referred to as AGND.

11. An internal Charge Pump and LDO (powered by CPVDD1) provide the Microphone Bias supply; the MICVDD pin should not be connected

to an external supply.

12. DCVDD and MICVDD minimum rise times do not apply when these domains are powered using the internal LDOs.

13. If DCVDD is supplied externally, and the rise time exceeds 2ms, then RESET

¯¯¯¯¯¯ must be asserted (low) during the rise, and held asserted

until after DCVDD is within the recommended operating limits.

14. LDOVDD maximum rise time does not apply when DCVDD is supplied externally.

15. If DCVDD is powered using the internal LDO (LDO1), and the LDOVDD rise time exceeds 50ms, then RESET

¯¯¯¯¯¯ must be asserted (low), or

LDOENA held low, during the rise. One or both these signals must be held low until after LDOVDD is within the recommended operating

limits.

16. The specified minimum power supply rise times assume a minimum decoupling capacitance of 100nF per pin. However, Cirrus Logic

strongly advises that the recommended decoupling capacitors are present on the PCB and that appropriate layout guidelines are observed.

17. The specified minimum power supply rise times also assume a maximum PCB inductance of 10nH between decoupling capacitor and pin.

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