CS47L85 datasheet(82/370 Pages) CIRRUS

82 / 370 page

CS47L85

Rev 4.3

DYNAMIC RANGE CONTROL (DRC)

The digital core provides two stereo Dynamic Range Control (DRC) processing blocks as illustrated in Figure 28. A 4-input

mixer is associated with each DRC input channel. The 4 input sources are selectable in each case, and independent volume

control is provided for each path. The stereo DRC blocks support 2 outputs each.

The function of the DRC is to adjust the signal gain in conditions where the input amplitude is unknown or varies over a wide

range, e.g. when recording from microphones built into a handheld system, or to restrict the dynamic range of an output

signal path.

The DRC can apply Compression and Automatic Level Control to the signal path. It incorporat

es ‘anti-clip’ and ‘quick release’

features for handling transients in order to improve intelligibility in the presence of loud impulsive noises.

The DRC also incorporates a Noise Gate function, which provides additional attenuation of very low-level input signals. This

means that the signal path is quiet when no signal is present, giving an improvement in background noise level under these

conditions.

A Signal Detect function is provided within the DRC; this can be used to detect the presence of an audio signal, and used

to trigger other events. The Signal Detect function can be used as an Interrupt event, or used to trigger the Control Write

Sequencer (note - DRC1 only).

DRCnLMIX_VOL2

DRCnLMIX_VOL3

DRCnLMIX_VOL4

DRCnLMIX_VOL1

DRCnLMIX_SRC1

DRCnLMIX_SRC3

DRCnLMIX_SRC4

DRCnLMIX_SRC2

DRC1 Left (58h)

DRC2 Left (5Ah)

DRC

Dynamic Range Controller

DRCnRMIX_VOL2

DRCnRMIX_VOL3

DRCnRMIX_VOL4

DRCnRMIX_VOL1

DRCnRMIX_SRC1

DRCnRMIX_SRC3

DRCnRMIX_SRC4

DRCnRMIX_SRC2

DRC1 Right (59h)

DRC2 Right (5Bh)

DRC

Dynamic Range Controller

CS47L85 supports 2 Stereo DRC blocks, ie. n = 1 or 2

Figure 28 Dynamic Range Control (DRC) Block

The DRC1 and DRC2 mixer control registers (see Figure 28) are located at register addresses R2240 (8C0h) through to

R2271 (08DFh).

The full list of digital mixer control registers (Register R1600 through to R3192) is provided in a separate document - see

“Register Map” for further information. Generic register definitions are provided in Table 8.

The *_SRCn registers select the input source(s) for the respective DRC processing blocks. Note that the selected input

source(s) must be configured for the same sample rate as the DRC to which they are connected. Sample rate conversion

functions are available to support flexible interconnectivity -

see “Asynchronous Sample Rate Converter (ASRC)” and

“Isochronous Sample Rate Converter (ISRC)”.

The bracketed numbers in Figure 28,

e.g.,”(58h)” indicate the corresponding *_SRCn register setting for selection of that

signal as an input to another digital core function.

The DRC blocks should be kept disabled (DRCnx_ENA=0) if SYSCLK is not enabled. The *_SRCn registers for all digital

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