CS47L85 datasheet(97/370 Pages) CIRRUS

97 / 370 page

CS47L85

Rev 4.3

The DSPn mixer / input control registers (see Figure 31) are located at register addresses R2368 (940h) through to R2676

(A74h).

The full list of digital mixer control registers (Register R1600 through to R3192) is provided in a separate document - see

“Register Map” for further information. Generic register definitions are provided in Table 8.

The *_SRCn registers select the input source(s) for the respective DSP processing blocks. Note that the selected input

source(s) must be configured for the same sample rate as the DSP to which they are connected. Sample rate conversion

functions are available to support flexible interconnectivity -

see “Asynchronous Sample Rate Converter (ASRC)” and

“Isochronous Sample Rate Converter (ISRC)”.

The bracketed numbers in Figure 31,

e.g.,”(68h)” indicate the corresponding *_SRCn register setting for selection of that

signal as an input to another digital core function.

The *_SRCn registers for all digital core functions should be held at 00h if SYSCLK is not enabled

– SYSCLK must be

present and enabled before selecting other

values for these registers. See “Clocking and Sample Rates” for further details

(including requirements for reconfiguring SYSCLK while digital core mixers are enabled).

The sample rate for each of the DSP functions is configured using the respective DSPn_RATE registers - see Table 22.

Sample rate conversion is required when routing the DSPn signal paths to any signal chain that is asynchronous and/or

configured for a different sample rate.

The DSPn_RATE registers should not be changed if any of the respective *_SRCn registers is non-zero. The associated

*_SRCn registers should be cleared to 00h before writing new values to DSPn_RATE. A minimum delay of 125us should

be allowed between clearing the *_SRCn registers and writing to the associated DSPn_RATE registers. See Table 22 for

further details.

The CS47L85 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the commanded

DSP mixing functions. If an attempt is made to enable a DSP mixer path, and there are insufficient SYSCLK cycles to support

it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these

circumstances.)

The status bits in Registers R1600 to R3192 indicate the status of each of the digital mixers. If an Underclocked Error

condition occurs, then these bits provide readback of which mixer(s) have been successfully enabled.

SPDIF OUTPUT GENERATOR

The CS47L85 incorporates an IEC-60958-3 compatible S/PDIF output generator, as illustrated in Figure 32; this provides a

stereo S/PDIF output on a GPIO pin. The S/PDIF transmitter allows full control over the S/PDIF validity bits and channel

status information.

The input sources to the S/PDIF transmitter are selectable for each channel, and independent volume control is provided

for each path. The *TX1 and *TX2 registers control channels ‘A’ and ‘B’ (respectively) of the S/PDIF output.

The S/PDIF signal can be output directly on a GPIO pin. See “General Purpose Input / Output” to configure a GPIO pin for

this function.

Note that the S/PDIF signal cannot be selected as input to the digital mixers or signal processing functions within the

CS47L85 digital core.

SPDIF1TX1_VOL

SPDIF1TX2_VOL

SPDIF1TX2_SRC

SPDIF1TX1_SRC

GPIO

(GPn_FN = 4Ch)

S/PDIF

SPD1_ENA

SPD1_RATE

Channel ‘A’

Channel ‘B’

Figure 32 Digital Core S/PDIF Output Generator

CS47L85 датащи(PDF) 97 Page - Cirrus Logic

CS47L85 датащи(HTML) 97 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL