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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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L9908 датащи(PDF) 87 Page - STMicroelectronics |
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L9908 датащи(HTML) 87 Page - STMicroelectronics |
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87 / 153 page  Note: • 00 and 01 configurations are intended to be used when the current to be read is only positive (DC-LINK configuration) • 10 and 11 configurations should be used when the current to be read is either positive or negative (Single Leg) The 11-bits unsigned word feeds a cascaded of a 10-bit resistive string DAC and a Voltage Buffer that converts the digital code into the corresponding analog signal referred to the full scale voltage. DRV gain can be configured by means of dedicated SPI bits in order to adjust the current monitor output range to the μC ADC input range as follows: Table 78. Current monitors output gain configuration CSM_OUT_RANGE_CFG Description 0 VCSO = 3.3 V (Default) 1 VCSO = 5 V To ensure output signal stability, a RC low-pass filter is recommended on CSOn pins; refer to Section 6 Application circuit and the related Section 6.3 Bill of materials for details. Table 79. Current monitor`s analog output characteristics Symbol Parameter Test Condition Min Typ Max Unit Notes Current Monitor Analog Output CM_out_range_max CSOn output range max Iload = 250 μA - - 0.11 V - CM_out_range_min CSOn output range min Iload = -250 μA CSMn_OUT_RANGE_CFG = 1 CSMn_OUT_RANGE_CFG = 0 4.8 3.28 - VDD 3.32 V - Current Monitor Analog Output Resolution CM_out__dac_res CM DAC resolution - - 11 - bits Design Information CM_out_dac_lsb CM DAC LSB - - 2.441 1.611 - mV Design Information Current Monitor Analog Output Dynamic Characteristics CM_out_dac_data_rate CM DAC sample rate - - 1.25 - MHz Application information CM_out_dac_pos_st1 CM DAC positive settling time 1 23 to 1023 LSB transition RLP = 1 kΩ CLP = 270 pF - - 0.8 μs - CM_out_dac_pos_st2 CM DAC positive settling time 2 1023 to 2048 LSB Transition RLP = 1 kΩ CLP = 270 pF - - 0.8 μs - CM_out_dac_neg_st1 CM DAC negative settling time 1 2048 to 1023 LSB transition RLP = 1 kΩ CLP = 270 pF - - 0.8 μs - CM_out_dac_neg_st2 CM DAC negative settling time 2 1023 to 23 LSB Transition RLP = 1 kΩ CLP = 270 pF - - 0.8 μs - L9908 Current monitors DS13546 - Rev 3 page 87/153 |
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