AD8384ASVZ datasheet(16/24 Pages) AD

16 / 24 page

AD8384

Rev. 0 | Page 16 of 24

ACCURACY

To best correlate transfer function errors to image artifacts, the

overall accuracy of the DecDriver is defined by two parameters:

VDE and VCME.

VDE, the differential error voltage, measures the difference

between the rms value of the output and the rms value of the

ideal. The defining expression is

VFS

VOUTP

VOUTN

VDE

⎟

⎠

⎞

⎜

⎝

⎛

1023

–

]

–

)

(

[

–

]

–

)

(

[

)

(

VCME, the common-mode error voltage, measures ½ the dc

bias of the output. The defining expression is

()

⎥

⎦

⎤

⎢

⎣

⎡

–

)

(

)

(

)

(

VOUTP

VOUTN

VCME

TSTM CONTROL—TEST MODE

A LOW on this input allows serial interface control of the

output operating mode. A HIGH on this input forces the video

outputs and VAO1 to normal operating mode.

GROUNDED OUTPUT MODE

In normal operating mode, the voltage of the video outputs and

VAO1 are determined by the inputs.

In Grounded Output mode, the video outputs and VAO1 are

forced to AGND.

OVERLOAD PROTECTION

The overload protection employs current limiters and a thermal

switch, protecting the video output pins against accidental

shorts between any video output pin and AVCC or AGND.

The junction temperature trip point of the thermal switch is

165°C. Production test guarantees a minimum junction

temperature trip point of 125°C. Consequently, the operating

junction temperature should not be allowed to rise above 125°C.

For systems that operate at high internal ambient temperatures

and require large capacitive loads to be driven by the AD8384 at

high frequencies, a minimum airflow of 200 lfm should be

maintained to ensure junction temperatures below 125°C.

3-WIRE SERIAL INTERFACE

The serial interface controls two 8-bit serial DACs, the overload

protection and the video output operating mode via a 12-bit

wide serial word from a microprocessor. Four of the 12-bits

select the function and the remaining eight bits are the data for

the serial DACs.

Table 12. Bit Definitions

Bit

Name

Bit Functionality

SD(0:7)

8-Bit SDAC Data. MSB = SD7.

SD8

Not Used.

SD9

Not Used.

SD10

Output operating mode and SDAC selection control.

SD11

Output operating mode and SDAC selection control.

Table 13. Truth Table

SEN

Action

Load VAO2. No change to VAO1. No

change to Grounded mode.

Load VAO1. Release outputs from

Grounded mode. No change to AO2.

Release Video Outputs and VAO1

from Grounded Output mode. No

change to VAO1 and VAO2 data.

Video Outputs and VAO1 to

Grounded Output mode. No change

to VAO1 and VAO2 data.

No Change.

SERIAL DACS

Both serial DACs are loaded via the serial interface. The output

voltage is determined by the following equation:

VAO1, VAO2 = SVRL + SD(0:7) × (SVRH – SVRL)/256

Output VAO1 is designed to drive very large capacitive loads

above 0.047 µF. Lower capacitive loads may result in excessive

overshoot at VAO1.

LEVEL SHIFTERS

The characteristics of the level shifters are optimized based on

their intended use.

Seven level shifters—DX, CLX, CLXN, and ENBX(1:4)—are

optimized for “X direction,” and three—DY, CLY, and CLYN—

are optimized for the “Y direction” control signals. One level

shifter, NRG, is designed to drive a large capacitive load and

optimized for an X direction control signal and two, DIRX and

DIRY are optimized for very low frequency control signals.

One level shifting edge detector, MONITI, MONITO, is

optimized to condition a synchronizing feedback reference

signal from the LCD.

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