AD8384

Rev. 0 | Page 9 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NC =

NO CONNECT

DGND

TSTM

CLK

XFR

STSQ

INV

R/L

E/O

SDI

SEN

SCL

NC

AGNDS

SVRL

SVRH

VAO1

VAO2

AVCCS

DIRXIN

DIRYIN

AGND0

VID0

AVCC0,1

VID1

AGND1,2

VID2

AVCC2,3

VID3

AGND3,4

VID4

AVCC4,5

VID5

AGND5

CLXN

CLX

ENBX4

ENBX3

ENBX2

ENBX1

DX

1

2

3

4

5

6

7

8

9

10

11

13

14

15

16

12

17

18

20

19

80 79 78 77 76

71 70 69 68 67 66 65

75 74 73 72

64 63 62 61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

AD8384

Figure 3. 80-Lead 12 mm × 12 mm TQFP E-Pad Pin Configuration

Table 7. Pin Function Descriptions

Pin Name

Function

Description

DB(0:9)

Data Input

10-Bit Data Input. MSB = DB(9).

CLK

Clock

Clock Input.

STSQ

Start Sequence

The state of STSQ is detected on the active edge of CLK. A new data loading sequence

begins on the next active edge of CLK after STSQ is detected HIGH.

The active CLK edge is the rising edge when E/O is held HIGH. It is the falling edge when

E/O is held LOW.

R/L

Right/Left Select

A new data loading sequence begins on the left, with Channel 0, when this input is LOW,

and on the right, with Channel 5, when this input is HIGH.

E/O

Even/Odd Select

The active CLK edge is the rising edge when this input is held HIGH. It is the falling edge

when this input is held LOW. Data is loaded sequentially on the rising edges of CLK when

this input is HIGH and on the falling edges when this input is LOW.

XFR

Data Transfer

XFR is detected and a data transfer is initiated on a rising CLK edge when this input is held

HIGH. Data is transferred to the video outputs on the next rising CLK edge after XFR is

detected.

VID0–VID5

Analog Outputs

These pins are directly connected to the analog inputs of the LCD panel.

V1, V2

Reference Voltages

The voltage applied between V1 and AGND sets the white video level during INV = LOW.

The voltage applied between V2 and AGND sets the white video level during INV = HIGH.

VRH, VRL

Full-Scale References

Twice the voltage applied between these pins sets the full-scale video output voltage.

BYP

Bypass

A 0.1µ F capacitor connected between this pin and AGND ensures optimum settling time.