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AD8384ASVZ датащи(PDF) 11 Page - Analog Devices

номер детали AD8384ASVZ
подробное описание детали  10-Bit, 6-Channel Decimating LCD DecDriver-R with Level Shifters
PDF  24 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD8384ASVZ датащи(HTML) 11 Page - Analog Devices

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AD8384
Rev. 0 | Page 11 of 24
TIMING CHARACTERISTICS
DECDRIVER SECTION
VRH VRL
VID2
VID3
VID4
VID5
VID1
VID0
AD8384
BYP
R/L
CLK
STSQ
XFR
INV
V1
V2
DB(0:9)
2-STAGE
2-STAGE
2-STAGE
2-STAGE
2-STAGE
2-STAGE
LATCH
LATCH
LATCH
LATCH
LATCH
LATCH
10
10
10
10
10
10
10
10
10
10
10
10
SCALING
CONTROL
SEQUENCE
INV CONTROL
CONTROL
BIAS
10
10
DAC
DAC
DAC
DAC
DAC
DAC
Figure 4. Block Diagram
tf
CLK
DB(0:9)
STSQ
XFR
VTH
VTH
VTH
VTH
tr
t8
t7
t2
t1
t4
t3
t6
t5
Figure 5. Input Timing, Even Mode (E/O = HIGH)
CLK
DB(0:9)
STSQ
XFR
VTH
VTH
VTH
VTH
t8
t7
t2
t1
t4
t3
t6
t5
Figure 6. Input Timing, Odd Mode ( E/O = LOW)
CLK
STSQ
XFR
INV
VID(0:5)
t10
t9
V2
50% PIXELS
–6,–5, –4,–3, –2,–1
V1
V1–VFS
V2+VFS
DB(0:9)
–1
0
1
2
3
4
5
7
6
–8
–7
–6
–5
–4
–2
–3
t9
50%
PIXELS 0, 1, 2, 3, 4, 5
Figure 7. Output Timing (R/L = Low, E/O = High)
Table 8. Timing Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
t1
CLK to Data Setup Time
0
ns
t2
CLK to Data Hold Time
3
ns
t3
CLK to STSQ Setup Time
0
ns
t4
CLK to STSQ Hold Time
3
ns
t5
CLK to XFR Setup Time
0
ns
t6
CLK to XFR Hold Time
3
ns
t7
CLK High Time
3
ns
t8
CLK Low Time
2.5
ns
t9
CLK to VIDx Delay
10
12
14
ns
t10
INV to VIDx Delay
13
15
17
ns



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