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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD8384ASVZ датащи(PDF) 6 Page - Analog Devices |
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AD8384ASVZ датащи(HTML) 6 Page - Analog Devices |
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6 / 24 page  AD8384 Rev. 0 | Page 6 of 24 SERIAL INTERFACE Table 4. @ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0°C, TA MAX = 85°C, SVRL = 4 V, SVRH = 9 V, unless otherwise noted Parameter Conditions Min Typ Max Unit SERIAL DAC REFERENCE INPUTS SVFS = (SVRH – SVRL) SVRH Range SVRL < SVRH SVRL + 1 AVCC – 3.5 V SVRL Range SVRL < SVRH AGND + 1.5 SVRH – 1 V SVFS Range 1 8 V SVRH Input Current SVFS = 5 V –70 nA SVRL Input Current SVFS = 5 V –2.8 –2.5 mA SVRH Input Resistance 40 kΩ SERIAL DAC ACCURACY DNL SVFS = 5 V, RL = ∞ –1.0 +1.0 LSB INL SVFS=5 V, RL = ∞ –1.5 +1.5 LSB Output Offset Error –2.0 +2.0 LSB Scale Factor Error –4.0 +4.0 LSB SERIAL DAC LOGIC INPUTS CIN 3 pF IIL –0.6 µA IIH 0.05 µA VTH 1.65 V VIH 2.0 DVCC V VIL DGND 0.8 V SERIAL DAC OUTPUTS Maximum Output Voltage SVRH – 1 LSB V Minimum Output Voltage SVRL V VAO1—Grounded Mode 0.1 V IOUT ±30 mA CLOAD Low Range6 0.002 µF CLOAD High Range1 0.047 µF SERIAL DAC DYNAMIC PERFORMANCE SEN to SCL Setup Time, t20 10 ns SCL, High Level Pulse Width, t21 15 ns SCL, Low Level Pulse Width, t22 10 ns SDI Setup Time, t24 10 ns SDI Hold Time, t25 10 ns SCL to SEN Hold Time, t23 15 ns VAO1, VAO2 Settling Time, t26 SVFS = 5 V, to 0.5%, CL = 100 pF 1 2 µs VAO1, VAO2 Settling Time, t26 SVFS = 5 V, to 0.5%, CL = 33 µF 10 15 ms 6 Outputs VAO1 and VAO2 are designed to drive very high capacitive loads. The load capacitance must be ≤ 0.002 µF or ≥0.047 µF. Load capacitance in the range 0.002 µF to 0.047 µF causes the output overshoot to exceed 100 mV. |
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